[PATCH] D133205: [AMDGPU][MC][GFX11][NFC] Update assembler tests for VOPD instructions

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added a comment.

In D133205#3772071 <https://reviews.llvm.org/D133205#3772071>, @foad wrote:

> In D133205#3772066 <https://reviews.llvm.org/D133205#3772066>, @dp wrote:
>
>> In D133205#3772014 <https://reviews.llvm.org/D133205#3772014>, @Joe_Nash wrote:
>>
>>>> We also need negative tests to check constant bus limitations and VGPR bank conflicts. These tests should be added separately.
>>>
>>> It would be good to have such tests, but the actual functionality to verify the constraints in the assembler would need to be added. We currently do not check those properties in the assembly, only during CodeGen.
>>
>> Thanks, I know that VOPD validation is missing in the assembler. I'm planning to add it.
>
> Is there any way that we can use the same validation code for both the assembler and SIInstrInfo::verifyInstruction?

IMO, this is hardly feasible because MC layer uses a different representation of instructions and operands than Codegen does. But we may be able to reuse some snippets of `SIInstrInfo::verifyInstruction` code.


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https://reviews.llvm.org/D133205