[PATCH] D130076: [llvm/CodeGen] Enable the ExpandLargeDivRem pass for X86, Arm and AArch64

[Matthias Gehre via Phabricator via llvm-commits]

mgehre-amd updated this revision to Diff 458108.
mgehre-amd added a comment.

- Simplified tests to only check for NOT: call

- Rebased on main

- Disable expand-large-div-rem when the second operand of div/rem is a power-of-two constant. For those, the backend has peephole optimizations, see llvm/test/CodeGen/X86/i128-sdiv.ll

- Updated new test since rebasing:
  - llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed/unsigned.ll, llvm/test/CodeGen/X86/i128-udiv/sdiv.ll: Those tests were checking that `call __divti3` was created on X86 for 128 bit divisions, which makes no sense because __divti3 is neither implemented by libgcc nor by compiler-rt on X86 in 32-bit mode.
  - Removed test llvm/test/CodeGen/X86/libcall-sret.ll: It was checking that the backend doesn't crash when emitting a 128 bit libcall on 32-bit X86. Now that we don't emit calls to __divti3 on X86 anymore, there is no 128 bit libcall left to reproduce the issue.
  - llvm/test/CodeGen/X86/pr38539.ll: Removed X86 section from f(); the comment says that f() is targeted at 64-bit mode- In 32 bit mode, we would now get a urem expansion.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130076/new/

https://reviews.llvm.org/D130076

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/CodeGen/ExpandLargeDivRem.cpp
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/test/CodeGen/AArch64/O0-pipeline.ll
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/udivmodei5.ll
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/ARM/udivmodei5.ll
  llvm/test/CodeGen/X86/O0-pipeline.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/X86/i128-sdiv.ll
  llvm/test/CodeGen/X86/i128-udiv.ll
  llvm/test/CodeGen/X86/libcall-sret.ll
  llvm/test/CodeGen/X86/opt-pipeline.ll
  llvm/test/CodeGen/X86/pr38539.ll
  llvm/test/CodeGen/X86/udivmodei5.ll

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