[PATCH] D133255: [RISCV] Transform VMERGE_VVM_<LMUL>_TU with all ones mask to VADD_VI_<LMUL>_TU.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 marked 2 inline comments as done.
fakepaper56 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2511
   // Check that we're using V0 as a mask register.
   if (!isa<RegisterSDNode>(N->getOperand(MaskOpIdx)) ||
       cast<RegisterSDNode>(N->getOperand(MaskOpIdx))->getReg() != RISCV::V0)
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kito-cheng wrote:
> fakepaper56 wrote:
> > Do we have an instruction that mask operand is not `v0`? I am confused by the condition. 
> We *might* allow mask hold other than `v0` register in future vector extension, so having this checking should be harmless, and could catch unexpected case in future.
Thank your explanation.


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  https://reviews.llvm.org/D133255/new/

https://reviews.llvm.org/D133255