[PATCH] D133214: [docs][RISCV] Document experimental extensions

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 2 09:06:04 PDT 2022


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This adds a description of the currently existing experimental extensions.  I took all information about versions and specifications from either the original commits, or current code.  I'm not terribly familiar with any of these, so double checking my facts is much appreciated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133214

Files:
  llvm/docs/RISCVUsage.rst


Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -73,6 +73,26 @@
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly tools (e.g. assembler, dissambler, llvm-objdump, etc..) don't have this restriction.
 
+Experimental Extensions
+=======================
+
+LLVM supports (to various degrees) a number of experimental extensions.  All experimental extensions have ``experimental-`` as a prefix.  There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised *not* to make use of experimental extensions before they reach ratification.
+
+The primary goal of experimental support is to assist in the process of ratification by providing an existance proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases.  Experimental extensions are expected to either transiiton to ratified status, or be eventually removed.  The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
+
+``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``, ``experimental-zbp``, ``experimental-zbr``, ``experimental-zbt``
+  LLVM implements the `latest state of the bitmanip working branch <https://github.com/riscv/riscv-bitmanip/tree/main-history>`_, which is largely similiar to the 0.93 draft specification but with some instruction naming changes.  These are individual portions of the bitmanpip efforts which did *not* get ratified.  Given ratification for these sub-extensions appears stalled; they are a likely candidate for removal in the future.
+
+``experimental-zca``
+  LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+
+``experimental-zihintntl``
+  LLVM implements the 0.2 draft specification.
+
+``experimental-zvfh``
+  LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
+
+
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International


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