[PATCH] D133199: [ARM] Constant pools need 4-byte alignment if we only have tADR

[John Brawn via Phabricator via llvm-commits]

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When the only ADR instruction we have is the 16-bit thumb one then all constant pool entries need to be 4-byte aligned, as tADR has an offset that's a multiple of 4.

It looks like previously there happened to be no situations in which we encountered a constant pool entry with alignment less than 4, so failing to do this didn't cause any problems, but the expansion of cttz to a table does use a constant pool with alignment 1, so we now need to handle it correctly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133199

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cttz.ll

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