[PATCH] D133063: [docs] Add a RISC-V Usage page

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


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Comment at: llvm/docs/RISCVUsage.rst:18
+
+The specification defines three base instruction sets: RV32I, RV64I, and RV128I.
+Currently, LLVM supports RV32I, and RV64I, but not RV128I.
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reames wrote:
> asb wrote:
> > I think RV32E is typically described as a base instruction set too (albeit one that is actually a subset of RV32I).
> Do we support RV32E?  You're right that this seems to be a base instruction set.  If we do support it, how do we name that argument wise?
> 
> For now, I updated the text to indicate we didn't support RV32E, but I'm unsure if this is correct.
RV32E is supported in MC-layer[1] but not CodeGen[2], and we have RV64E ISA[2] now, that should be worth to mention that we are not support that here.

[1] https://reviews.llvm.org/D59470
[2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L53
[2] https://github.com/riscv/riscv-isa-manual/commit/b5f94a845760af00ff2743dd9f2269fd68236576


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Comment at: llvm/docs/RISCVUsage.rst:64
+     ``Zve64d``     Supported
+     ``Zvl32b``     Unsupported
+     ``Zvl64b``     Supported
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reames wrote:
> kito-cheng wrote:
> > Maybe mark as MC-layer only?
> Is it even supported by assembler?  It could be, but I hadn't thought to check.  
`Zvl32b` isn't define any instruction or CSRs, just a information about the VLEN is larger than 32 bits.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063