[llvm] 11881a8 - [RISCV] Rename some V extension multiclasses for consistency. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 1 22:17:32 PDT 2022
Author: Craig Topper
Date: 2022-09-01T22:17:08-07:00
New Revision: 11881a8f3f128de1093f8e24ce26b2a440222a28
URL: https://github.com/llvm/llvm-project/commit/11881a8f3f128de1093f8e24ce26b2a440222a28
DIFF: https://github.com/llvm/llvm-project/commit/11881a8f3f128de1093f8e24ce26b2a440222a28.diff
LOG: [RISCV] Rename some V extension multiclasses for consistency. NFC
Use "SDNode" in the name is the convention for the VLMax patterns
in RISCVInstrInfoVSDPatterns.td. This files use "VL".
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 0202ca5c5b89a..44e977c232bc9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -619,8 +619,8 @@ multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc,
}
}
-multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
- list <VTypeInfoToFraction> fraction_list> {
+multiclass VPatExtendVL_V<SDNode vop, string inst_name, string suffix,
+ list <VTypeInfoToFraction> fraction_list> {
foreach vtiTofti = fraction_list in {
defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti;
@@ -633,7 +633,7 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
}
}
-multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatConvertFP2IVL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
@@ -645,7 +645,7 @@ multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
}
}
-multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatConvertI2FPVL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
@@ -657,7 +657,7 @@ multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
}
}
-multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatWConvertFP2IVL_V<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
@@ -670,7 +670,7 @@ multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
}
}
-multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatWConvertI2FPVL_V<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar ivti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
@@ -683,7 +683,7 @@ multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
}
}
-multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatNConvertFP2IVL_V<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
@@ -696,7 +696,7 @@ multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
}
}
-multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
+multiclass VPatNConvertI2FPVL_V<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
@@ -731,7 +731,7 @@ multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
}
}
-multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
+multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
@@ -756,9 +756,9 @@ multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruc
}
}
-multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> {
- defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>;
- defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>;
+multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {
+ defm : VPatBinaryExtVL_WV_WX<op, sext_oneuse, instruction_name>;
+ defm : VPatBinaryExtVL_WV_WX<op, zext_oneuse, instruction_name>;
foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
@@ -1046,18 +1046,18 @@ defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSU
defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">;
// 12.3. Vector Integer Extension
-defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2",
- AllFractionableVF2IntVectors>;
-defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2",
- AllFractionableVF2IntVectors>;
-defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4",
- AllFractionableVF4IntVectors>;
-defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4",
- AllFractionableVF4IntVectors>;
-defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8",
- AllFractionableVF8IntVectors>;
-defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8",
- AllFractionableVF8IntVectors>;
+defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2",
+ AllFractionableVF2IntVectors>;
+defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF2",
+ AllFractionableVF2IntVectors>;
+defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF4",
+ AllFractionableVF4IntVectors>;
+defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF4",
+ AllFractionableVF4IntVectors>;
+defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF8",
+ AllFractionableVF8IntVectors>;
+defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF8",
+ AllFractionableVF8IntVectors>;
// 12.5. Vector Bitwise Logical Instructions
defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">;
@@ -1079,8 +1079,8 @@ foreach vti = AllIntegerVectors in {
}
// 12.7. Vector Narrowing Integer Right Shift Instructions
-defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">;
-defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">;
+defm : VPatBinaryVL_WV_WX_WI<srl, "PseudoVNSRL">;
+defm : VPatBinaryVL_WV_WX_WI<sra, "PseudoVNSRA">;
defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">;
defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">;
@@ -1471,16 +1471,16 @@ foreach fvti = AllFloatVectors in {
GPR:$vl, fvti.Log2SEW)>;
// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
- defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">;
- defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">;
- defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
- defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
+ defm : VPatConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">;
+ defm : VPatConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">;
+ defm : VPatConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
+ defm : VPatConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
- defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">;
- defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
- defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
- defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;
+ defm : VPatWConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">;
+ defm : VPatWConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
+ defm : VPatWConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
+ defm : VPatWConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
@@ -1493,10 +1493,10 @@ foreach fvti = AllFloatVectors in {
}
// 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions
- defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">;
- defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
- defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
- defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
+ defm : VPatNConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">;
+ defm : VPatNConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
+ defm : VPatNConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
+ defm : VPatNConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
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