[PATCH] D133169: [AMDGPU] Constrain src0 RC of 64 bit shift amount on gfx90a

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: kerbowa, vangthao, bcahoon, cfang, b-sumner.
Herald added subscribers: kosarev, foad, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm, qcolombet, MatzeB.
Herald added a project: All.
rampitec requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

This is another w/a for the bug where a shift amount cannot be
a highest allocated register. Unlike D133067 <https://reviews.llvm.org/D133067> this w/a is not
guaranteed as later passes may replace the operand or whole
instruction, but works most of the times. Thus making D133067 <https://reviews.llvm.org/D133067>
not unneeded but less likely to trigger and hopefully resulting
in a better code.


https://reviews.llvm.org/D133169

Files:
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/hazard-shift64.ll
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D133169.457443.patch
Type: text/x-patch
Size: 17764 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220901/a1787101/attachment-0001.bin>