[llvm] b9062ce - [AArch64][SVE] Add floating-point repeated complex pattern llc tests

[Matt Devereau via llvm-commits]

Author: Matt Devereau
Date: 2022-09-01T15:04:59Z
New Revision: b9062ceffc4d5878d95831908a851038fdadb310

URL: https://github.com/llvm/llvm-project/commit/b9062ceffc4d5878d95831908a851038fdadb310
DIFF: https://github.com/llvm/llvm-project/commit/b9062ceffc4d5878d95831908a851038fdadb310.diff

LOG: [AArch64][SVE] Add floating-point repeated complex pattern llc tests

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
index 810fa5ef830d..7b31f0e7f6d4 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -584,6 +584,54 @@ define <vscale x 2 x i64> @dupq_i64_range(<vscale x 2 x i64> %a) {
 ; EXT
 ;
 
+define dso_local <vscale x 4 x float> @dupq_f32_repeat_complex(float %x, float %y) {
+; CHECK-LABEL: dupq_f32_repeat_complex:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    mov v2.16b, v0.16b
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    mov v2.s[1], v1.s[0]
+; CHECK-NEXT:    mov v2.s[2], v0.s[0]
+; CHECK-NEXT:    mov v2.s[3], v1.s[0]
+; CHECK-NEXT:    mov z0.q, q2
+; CHECK-NEXT:    ret
+  %1 = insertelement <4 x float> undef, float %x, i64 0
+  %2 = insertelement <4 x float> %1, float %y, i64 1
+  %3 = insertelement <4 x float> %2, float %x, i64 2
+  %4 = insertelement <4 x float> %3, float %y, i64 3
+  %5 = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %4, i64 0)
+  %6 = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %5, i64 0)
+  ret <vscale x 4 x float> %6
+}
+
+define dso_local <vscale x 8 x half> @dupq_f16_repeat_complex(half %a, half %b) {
+; CHECK-LABEL: dupq_f16_repeat_complex:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $q0
+; CHECK-NEXT:    mov v2.16b, v0.16b
+; CHECK-NEXT:    // kill: def $h1 killed $h1 def $q1
+; CHECK-NEXT:    mov v2.h[1], v1.h[0]
+; CHECK-NEXT:    mov v2.h[2], v0.h[0]
+; CHECK-NEXT:    mov v2.h[3], v1.h[0]
+; CHECK-NEXT:    mov v2.h[4], v0.h[0]
+; CHECK-NEXT:    mov v2.h[5], v1.h[0]
+; CHECK-NEXT:    mov v2.h[6], v0.h[0]
+; CHECK-NEXT:    mov v2.h[7], v1.h[0]
+; CHECK-NEXT:    mov z0.q, q2
+; CHECK-NEXT:    ret
+  %1 = insertelement <8 x half> undef, half %a, i64 0
+  %2 = insertelement <8 x half> %1, half %b, i64 1
+  %3 = insertelement <8 x half> %2, half %a, i64 2
+  %4 = insertelement <8 x half> %3, half %b, i64 3
+  %5 = insertelement <8 x half> %4, half %a, i64 4
+  %6 = insertelement <8 x half> %5, half %b, i64 5
+  %7 = insertelement <8 x half> %6, half %a, i64 6
+  %8 = insertelement <8 x half> %7, half %b, i64 7
+  %9 = tail call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> %8, i64 0)
+  %10 = tail call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %9, i64 0)
+  ret <vscale x 8 x half> %10
+}
+
 define <vscale x 16 x i8> @ext_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
 ; CHECK-LABEL: ext_i8:
 ; CHECK:       // %bb.0: