[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

So I think I found a solution that may work. The idea is just to:

- Remove the SDag changes
  - After digging deep, I found that the InstrEmitter is smart enough to infer that the returned i1 is the implicit def of the instruction. No changes needed so.
  - However, it incorrectly assigns VReg_1 for the register class of the VCC copy it emits in InstrEmitter. This can be fixed in a pass.
- Add a small pass that runs before FixSGPRCopies that fixes the COPY of the implicit def for V_DIV_SCALE. Something like "FixVCCImpDefCopy". The pass itself is minimal and the logic boils down to:

  // Iterate over all instructions, check opcode
        case AMDGPU::V_DIV_SCALE_F32_e64:
        case AMDGPU::V_DIV_SCALE_F64_e64: {
          TII->fixImplicitOperands(MI);
  
          // Check for COPY of VCC right after it and fix it too.
          auto NextI = std::next(I);
          if(NextI == MBB->end() || NextI->getOpcode() != AMDGPU::COPY ||
              NextI->getOperand(1).getReg() != AMDGPU::VCC) {
            break;
          }
  
          if(TII->isWave32()) {
            NextI->getOperand(1).setReg(AMDGPU::VCC_LO);
            MRI->setRegClass(NextI->getOperand(0).getReg(), &AMDGPU::SReg_32_XM0_XEXECRegClass);
          } else {
            MRI->setRegClass(NextI->getOperand(0).getReg(), &AMDGPU::SReg_64_XEXECRegClass);
          }
        }

@foad, @rampitec do you think it's an acceptable solution? I can get all tests to pass with a seemingly normal codegen with that.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959