[PATCH] D132559: [AArch64] Add support for 128-bit non temporal loads.

[Zain Jaffal via Phabricator via llvm-commits]

zjaffal updated this revision to Diff 457201.
zjaffal added a comment.

Address some of the failing tests. The problem we have here is that all 128-bit vector loads will go to `LowerLOAD` function. 
Most of the failing test cases where triggered by the following assert

   assert((VT == MVT::v4i16 || VT == MVT::v4i32) && "Expected v4i16 or v4i32"); ``` To address this I added a block before it to return an empty `SDValue` node. Some tests 
  still fail after this fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132559/new/

https://reviews.llvm.org/D132559

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/nontemporal-load.ll

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