[llvm] c45810f - [RISCV] When ISD::SETUGT && Imm == -1, has processed before lowering

[via llvm-commits]

Author: liqinweng
Date: 2022-09-01T15:38:16+08:00
New Revision: c45810f81079bf35818baef248ebf37428d228b7

URL: https://github.com/llvm/llvm-project/commit/c45810f81079bf35818baef248ebf37428d228b7
DIFF: https://github.com/llvm/llvm-project/commit/c45810f81079bf35818baef248ebf37428d228b7.diff

LOG: [RISCV] When ISD::SETUGT && Imm == -1, has processed before lowering

When ISD::SETUGT && Imm == -1, has processed before lowering. Use assert replace it

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132373

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 32e794fbb077..961dc06e492b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3633,10 +3633,9 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       if (isa<ConstantSDNode>(RHS)) {
         int64_t Imm = cast<ConstantSDNode>(RHS)->getSExtValue();
         if (Imm != 0 && isInt<12>((uint64_t)Imm + 1)) {
-          // If this is an unsigned compare and the constant is -1, incrementing
-          // the constant would change behavior. The result should be false.
-          if (CCVal == ISD::SETUGT && Imm == -1)
-            return DAG.getConstant(0, DL, VT);
+          // X > -1 should have been replaced with false.
+          assert((CCVal != ISD::SETUGT || Imm != -1) &&
+                 "Missing canonicalization");
           // Using getSetCCSwappedOperands will convert SET(U)GT->SET(U)LT.
           CCVal = ISD::getSetCCSwappedOperands(CCVal);
           SDValue SetCC = DAG.getSetCC(