[PATCH] D132447: AMDGPU: Add a pass to fix SGPR liveness

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp:17
+///
+/// BB1 ends with a divergent branch. The virtual registers shown in above
+/// example are dead in BB2. After register allocation, they may end up
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ruiling wrote:
> foad wrote:
> > The implementation does not check that there is a divergent branch, so it would do the same thing for uniform control flow.
> Sounds true, this is doing things conservative, but I think it may not cause any regression in real case. Practically, such kind of pattern in source program should already been optimized into the single dominate value. The only possible cases that I can think of are either "opt-none" or "created by structurizeCFG". If such pattern is created by structurizeCFG, BB1 will be very likely to be divergent because structurizeCFG was designed to try to skip uniform branching as much as possible. I am not sure if checking the terminator of BB1 against s_cbranch_scc0/scc1 for uniform branch sounds good idea?
I will try to use the idea at https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp#L170 to detect divergent branch.


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  https://reviews.llvm.org/D132447/new/

https://reviews.llvm.org/D132447