[PATCH] D133063: [docs] Add a RISC-V Usage page

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/docs/RISCVUsage.rst:73
+Zve32x, Zve32f, Zvl32b
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bytes.
+
----------------
bytes -> bits


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063