[llvm] 86b6b39 - [llvm][test] precommit test for D130127

[Nick Desaulniers via llvm-commits]

Author: Nick Desaulniers
Date: 2022-08-31T12:40:52-07:00
New Revision: 86b6b394114145b2b47b55fbff934ad1bfbdef4e

URL: https://github.com/llvm/llvm-project/commit/86b6b394114145b2b47b55fbff934ad1bfbdef4e
DIFF: https://github.com/llvm/llvm-project/commit/86b6b394114145b2b47b55fbff934ad1bfbdef4e.diff

LOG: [llvm][test] precommit test for D130127

Add a FIXME that will be immediately removed in D130127.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D132609

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/tail-dup-asm-goto.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
index 9e3a8e605cfd..da8e0b6c823a 100644
--- a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
+++ b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication \
+; RUN:   -verify-machineinstrs=0 < %s | FileCheck %s
 
 ; Ensure that we don't duplicate a block with an "INLINEASM_BR" instruction
 ; during code gen.
@@ -69,3 +70,85 @@ bb17.i.i.i:                                       ; preds = %bb110
 kmem_cache_has_cpu_partial.exit:                  ; preds = %bb110
   ret ptr %i10.1
 }
+
+; The intent of this test is to test what happens when we have a callbr where
+; BOTH the fallthrough/direct target and the indirect target are the same basic
+; block. We might one day permit tail duplication here, but we need to ensure
+; that we don't crash or run afoul of any MachineVerifier checks.
+; FIXME: enable -verify-machineinstrs for this test!
+define void @ceph_con_v2_try_read(i32 %__trans_tmp_3.sroa.0.0.copyload, i1 %tobool.not.i.i) nounwind {
+  ; CHECK-LABEL: name: ceph_con_v2_try_read
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $edi, $esi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $esi
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edi
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.for.cond:
+  ; CHECK-NEXT:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   TEST32rr [[COPY1]], [[COPY1]], implicit-def $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.sw.bb:
+  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit
+  ; CHECK-NEXT:   [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0.skip.i.i, 1, $noreg, 0, $noreg
+  ; CHECK-NEXT:   $rdi = COPY [[LEA64r]]
+  ; CHECK-NEXT:   CALL64r killed [[SUBREG_TO_REG]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
+  ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $eax
+  ; CHECK-NEXT:   TEST8ri [[COPY2]], 1, implicit-def $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.4, 4, implicit $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.if.else.i.i:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 1 /* sideeffect attdialect */, 13 /* imm */, %bb.5
+  ; CHECK-NEXT:   LIFETIME_END %stack.0.skip.i.i
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.process_message_header.exit.i:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   LIFETIME_END %stack.0.skip.i.i
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.if.end.i (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   LIFETIME_END %stack.0.skip.i.i
+  ; CHECK-NEXT:   JMP_1 %bb.1
+entry:
+  %skip.i.i = alloca i32, i32 0, align 4
+  %cond = icmp eq i32 %__trans_tmp_3.sroa.0.0.copyload, 0
+  br label %for.cond
+
+for.cond:
+  br i1 %cond, label %sw.bb, label %for.cond
+
+sw.bb:
+  %call.i.i2 = call i32 null(ptr %skip.i.i)
+  br i1 %tobool.not.i.i, label %if.else.i.i, label %process_message_header.exit.i
+
+if.else.i.i:
+  callbr void asm sideeffect "", "!i"()
+          to label %if.end.i [label %if.end.i]
+
+process_message_header.exit.i:
+  call void @llvm.lifetime.end.p0(i64 0, ptr %skip.i.i)
+  br label %for.cond
+
+if.end.i:
+  call void @llvm.lifetime.end.p0(i64 0, ptr %skip.i.i)
+  br label %for.cond
+}
+
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)