[llvm] eaede4b - [DAG] extractShiftForRotate - replace assertion for shift opcode with an early-out

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-08-31T15:50:48+01:00
New Revision: eaede4b5b7cfc13ca0e484b4cb25b2f751d86fd9

URL: https://github.com/llvm/llvm-project/commit/eaede4b5b7cfc13ca0e484b4cb25b2f751d86fd9
DIFF: https://github.com/llvm/llvm-project/commit/eaede4b5b7cfc13ca0e484b4cb25b2f751d86fd9.diff

LOG: [DAG] extractShiftForRotate - replace assertion for shift opcode with an early-out

We feed the result from the first extractShiftForRotate call into the second, and that result might no longer be a shift op (usually due to constant folding).

NOTE: We REALLY need to stop creating nodes on the fly inside extractShiftForRotate!

Fixes Issue #57474

Added: 
    llvm/test/CodeGen/X86/pr57474.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index fd5c17257115a..d2640b6eda0fc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7232,9 +7232,8 @@ static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift,
                                      SDValue ExtractFrom, SDValue &Mask,
                                      const SDLoc &DL) {
   assert(OppShift && ExtractFrom && "Empty SDValue");
-  assert(
-      (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&
-      "Existing shift must be valid as a rotate half");
+  if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL)
+    return SDValue();
 
   ExtractFrom = stripConstantMask(DAG, ExtractFrom, Mask);
 

diff  --git a/llvm/test/CodeGen/X86/pr57474.ll b/llvm/test/CodeGen/X86/pr57474.ll
new file mode 100644
index 0000000000000..b12b7ee475861
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr57474.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define void @PR57474() nounwind {
+; CHECK-LABEL: PR57474:
+; CHECK:       # %bb.0: # %BB
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    movq %rsp, %rax
+; CHECK-NEXT:    leaq -16(%rax), %rsp
+; CHECK-NEXT:    movw $-32768, -16(%rax) # imm = 0x8000
+; CHECK-NEXT:    movq %rbp, %rsp
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+BB:
+  br label %BB1
+
+BB1:                                              ; preds = %BB
+  %A = alloca <1 x i16>, align 2
+  %L1 = load <1 x i16>, <1 x i16>* %A, align 2
+  %I = insertelement <1 x i16> %L1, i16 -1, i16 0
+  %B6 = add <1 x i16> %I, %I
+  %B3 = srem <1 x i16> %B6, %I
+  %B1 = add <1 x i16> %B3, %B3
+  %B5 = sdiv <1 x i16> %B1, %I
+  %B4 = udiv <1 x i16> %B3, <i16 -32768>
+  %B2 = or <1 x i16> %B4, %B5
+  %B = lshr <1 x i16> <i16 -32768>, %B2
+  store <1 x i16> %B, <1 x i16>* %A, align 2
+  ret void
+}