[PATCH] D132959: skip custom-lowering for v1f64 to be expanded instead, because it has only one lane

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/include/llvm/Support/MachineValueType.h:149
       v256f16        =  88,   //  256 x f16
-      v512f16        =  89,   //  256 x f16
+      v512f16        =  89,   //  512 x f16
 
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Good spot!


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:205
 ; No single instruction NEON support. Use SVE.
-define double @fadda_v1f64(double %start, <1 x double> %a) vscale_range(2,0) #0 {
+define double @fadda_v1f64(double %start, <1 x double> %a) vscale_range(1,0) #0 {
 ; CHECK-LABEL: fadda_v1f64:
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I think changing the vscale_range to be (1, 0) makes sense given the size of the types we're dealing with, however we'd normally do this in a separate standalone patch because there are now two things being changed here:

1. Changing the lowering to ignore v1f64 types for ISD::VECREDUCE_SEQ_FADD, and
2. Changing the vscale_range.

Ideally we'd want to see the effect on the test @fadda_v1f64 by having 1) only.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132959/new/

https://reviews.llvm.org/D132959