[PATCH] D132994: [RISC-V][HWASAN] Update memaccess test with proper checks

[Alexey Baturo via Phabricator via llvm-commits]

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[8/12] patch series to port HWASAN for riscv64


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132994

Files:
  llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll


Index: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
===================================================================
--- llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
+++ llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no-generate-body-for-unused-prefixes
 ; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefixes=CHECK,NOPIC %s
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck --check-prefixes=CHECK,PIC %s
 
@@ -20,6 +20,8 @@
 
 declare void @llvm.hwasan.check.memaccess.shortgranules(i8*, i8*, i32)
 
+; Below is a manually written checks
+; UTC_ARGS: --disable
 ; CHECK: .section        .text.hot,"axG", at progbits,__hwasan_check_x10_2_short,comdat
 ; CHECK-NEXT: .type   __hwasan_check_x10_2_short, at function
 ; CHECK-NEXT: .weak   __hwasan_check_x10_2_short
@@ -55,6 +57,3 @@
 ; PIC-NEXT: auipc   t1, %got_pcrel_hi(__hwasan_tag_mismatch_v2)
 ; PIC-NEXT: ld      t1, %pcrel_lo(.Lpcrel_hi0)(t1)
 ; CHECK-NEXT: jr      t1
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NOPIC: {{.*}}
-; PIC: {{.*}}


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