[PATCH] D132987: [PPC] Add RM as call preserved register

[Guozhi Wei via Phabricator via llvm-commits]

Carrot created this revision.
Carrot added reviewers: kbarton, nemanjai.
Herald added subscribers: shchenz, hiraditya.
Herald added a project: All.
Carrot requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

RM is a call preserved register, but it is missed in current call regmask. This patch adds it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132987

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/nofpexcept.ll


Index: llvm/test/CodeGen/PowerPC/nofpexcept.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/nofpexcept.ll
+++ llvm/test/CodeGen/PowerPC/nofpexcept.ll
@@ -133,7 +133,7 @@
   ; CHECK-NEXT:   $f2 = COPY [[COPY3]]
   ; CHECK-NEXT:   $f3 = COPY [[PHI]]
   ; CHECK-NEXT:   $f4 = COPY [[XXLXORdpz]]
-  ; CHECK-NEXT:   BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
+  ; CHECK-NEXT:   BL8_NOP &__gcc_qsub, csr_ppc64_altivec_rm, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
   ; CHECK-NEXT:   ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
   ; CHECK-NEXT:   [[COPY14:%[0-9]+]]:f8rc = COPY $f1
   ; CHECK-NEXT:   [[COPY15:%[0-9]+]]:f8rc = COPY $f2
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -312,9 +312,9 @@
 
   if (TM.isPPC64())
     return Subtarget.pairedVectorMemops()
-               ? CSR_SVR464_VSRP_RegMask
-               : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
-                                         : CSR_PPC64_RegMask);
+               ? CSR_SVR464_VSRP_RM_RegMask
+               : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RM_RegMask
+                                         : CSR_PPC64_RM_RegMask);
   else
     return Subtarget.pairedVectorMemops()
                ? CSR_SVR432_VSRP_RegMask
Index: llvm/lib/Target/PowerPC/PPCCallingConv.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -301,9 +301,10 @@
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
                                    )>;
-
+def CSR_PPC64_RM : CalleeSavedRegs<(add CSR_PPC64, RM)>;
 
 def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>;
+def CSR_PPC64_Altivec_RM : CalleeSavedRegs<(add CSR_PPC64_Altivec, RM)>;
 
 def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>;
 
@@ -373,6 +374,7 @@
 def CSR_SVR432_VSRP : CalleeSavedRegs<(add CSR_SVR432_Altivec, CSR_VSRP)>;
 
 def CSR_SVR464_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
+def CSR_SVR464_VSRP_RM : CalleeSavedRegs<(add CSR_SVR464_VSRP, RM)>;
 
 def CSR_SVR464_R2_VSRP : CalleeSavedRegs<(add CSR_SVR464_VSRP, X2)>;
 


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