[PATCH] D132981: [MachineCSE] Use TargetInstrInfo::isAsCheapAsAMove in isPRECandidate.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: efriedma, reames, anton-afanasyev.
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Some targets like RISC-V require operands to be inspected to
determine if an instruction is similar to a move.

Spotted while investigating code differences between using an ADDI
vs an ADDIW. RISC-V has the isAsCheapAsAMove flag for ADDI, but
the TII hook checks the immediate is 0 or the register is X0. ADDIW
is never generated with X0 or with an immediate of 0 so it doesn't
have the isAsCheapAsAMove flag.

I don't know enough about the PRE code to write a test for this yet.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132981

Files:
  llvm/lib/CodeGen/MachineCSE.cpp


Index: llvm/lib/CodeGen/MachineCSE.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCSE.cpp
+++ llvm/lib/CodeGen/MachineCSE.cpp
@@ -789,7 +789,7 @@
   if (!isCSECandidate(MI) ||
       MI->isNotDuplicable() ||
       MI->mayLoad() ||
-      MI->isAsCheapAsAMove() ||
+      TII->isAsCheapAsAMove(*MI) ||
       MI->getNumDefs() != 1 ||
       MI->getNumExplicitDefs() != 1)
     return false;


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