[llvm] 4df696f - [NFC] Move a test case across files.

[Mingming Liu via llvm-commits]

Author: Mingming Liu
Date: 2022-08-30T14:16:28-07:00
New Revision: 4df696fbe9ae872c5d1813d516c233cd3c11b64e

URL: https://github.com/llvm/llvm-project/commit/4df696fbe9ae872c5d1813d516c233cd3c11b64e
DIFF: https://github.com/llvm/llvm-project/commit/4df696fbe9ae872c5d1813d516c233cd3c11b64e.diff

LOG: [NFC] Move a test case across files.

The test case is about pmull2 instruction generated used than a SIMD
ldr being generated. So aarch64-pmull2.ll is a better test file.

Differential Revision: https://reviews.llvm.org/D132277

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
    llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll b/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
index e28041edbd89..a1997f2b774c 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
@@ -60,4 +60,19 @@ define void @test2(ptr %0, <2 x i64> %1, <2 x i64> %2) {
   ret void
 }
 
+; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.
+; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.
+define void @test3(ptr %0, <2 x i64> %1, i64 %2) {
+; CHECK-LABEL: test3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    dup v1.2d, x1
+; CHECK-NEXT:    pmull2 v0.1q, v0.2d, v1.2d
+; CHECK-NEXT:    str q0, [x0]
+; CHECK-NEXT:    ret
+  %4 = extractelement <2 x i64> %1, i64 1
+  %5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
+  store <16 x i8> %5, ptr %0, align 16
+  ret void
+}
+
 declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)

diff  --git a/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll b/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
index 8e8f0c1d21ff..55f1ad9b2e1e 100644
--- a/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
+++ b/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
@@ -62,19 +62,4 @@ define void @test3(ptr %0, i64 %1, i64 %2, i64 %3) {
   ret void
 }
 
-; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.
-; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.
-define void @test4(ptr %0, <2 x i64> %1, i64 %2) {
-; CHECK-LABEL: test4:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    dup v1.2d, x1
-; CHECK-NEXT:    pmull2 v0.1q, v0.2d, v1.2d
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
-  %4 = extractelement <2 x i64> %1, i64 1
-  %5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
-  store <16 x i8> %5, ptr %0, align 16
-  ret void
-}
-
 declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)