[llvm] 3e39ab2 - [AMDGPU][GFX11] Fix dst register class for V_CVT_U32_U16

[Joe Nash via llvm-commits]

Author: Joe Nash
Date: 2022-08-30T14:01:25-04:00
New Revision: 3e39ab25e6cc912f211bbe42950ebe71103dad54

URL: https://github.com/llvm/llvm-project/commit/3e39ab25e6cc912f211bbe42950ebe71103dad54
DIFF: https://github.com/llvm/llvm-project/commit/3e39ab25e6cc912f211bbe42950ebe71103dad54.diff

LOG: [AMDGPU][GFX11] Fix dst register class for V_CVT_U32_U16

This instruction was referring to the wrong VOPProfile, likely due to a
typo, leading to an incorrect destination register type.

The MC layer will care about this change, but is NFC while 16-bit values
actually use 32 bit registers.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D132878

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP1Instructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 8df67c7715573..68f38fefe7e49 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -586,7 +586,7 @@ let SubtargetPredicate = isGFX11Plus in {
                                       /*VOP1Only=*/ 1>;
   defm V_NOT_B16        : VOP1Inst<"v_not_b16", VOP_I16_I16>;
   defm V_CVT_I32_I16    : VOP1Inst<"v_cvt_i32_i16", VOP_I32_I16>;
-  defm V_CVT_U32_U16    : VOP1Inst<"v_cvt_u32_u16", VOP_I16_I16>;
+  defm V_CVT_U32_U16    : VOP1Inst<"v_cvt_u32_u16", VOP_I32_I16>;
 } // End SubtargetPredicate = isGFX11Plus
 
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