[PATCH] D132878: [AMDGPU][GFX11] Fix dst register class for V_CVT_U32_U16

Tue Aug 30 11:31:49 PDT 2022

Joe_Nash added a comment.

In D132878#3757923 <https://reviews.llvm.org/D132878#3757923>, @foad wrote:

> In D132878#3756416 <https://reviews.llvm.org/D132878#3756416>, @Joe_Nash wrote:
>
>> This instruction may not even be being used. Did we forget to implement an ISel pattern?
>
> I'm not sure "forget" is the right word. Without True16 this, instruction is of marginal utility, it's just a slightly shorter encoding of an AND with 0xFFFF. Even with True16 it's not necessary, since you could always use either an AND or a LSHR by 16, but I suppose having a single instruction for both cases is nice for readability.

Ok, thanks for that explanation. I was wondering how this instruction would be used. I will commit this to fix the obvious mistake.

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  https://reviews.llvm.org/D132878/new/

https://reviews.llvm.org/D132878