[llvm] 40999cb - [SVE] Fix SVEDup0 matching -0.0f
Stephen Long via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 30 11:07:46 PDT 2022
Author: Stephen Long
Date: 2022-08-30T11:07:17-07:00
New Revision: 40999cbd93795fb928ff1e0d48bd74377218651a
URL: https://github.com/llvm/llvm-project/commit/40999cbd93795fb928ff1e0d48bd74377218651a
DIFF: https://github.com/llvm/llvm-project/commit/40999cbd93795fb928ff1e0d48bd74377218651a.diff
LOG: [SVE] Fix SVEDup0 matching -0.0f
Because of D128669, CPY is being used to zero active lanes even in the case of -0.0f. This patch checks for floating point positive zero. That way SVEDup0 won't match -0.0f.
Fixes https://github.com/llvm/llvm-project/issues/57428
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D132880
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index b933b12e64983..5f3b2950ff864 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -183,12 +183,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
case AArch64ISD::DUP:
case ISD::SPLAT_VECTOR: {
auto Opnd0 = N->getOperand(0);
- if (auto CN = dyn_cast<ConstantSDNode>(Opnd0))
- if (CN->isZero())
- return true;
- if (auto CN = dyn_cast<ConstantFPSDNode>(Opnd0))
- if (CN->isZero())
- return true;
+ if (isNullConstant(Opnd0))
+ return true;
+ if (isNullFPConstant(Opnd0))
+ return true;
break;
}
default:
@@ -203,12 +201,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
case AArch64ISD::DUP:
case ISD::SPLAT_VECTOR: {
auto Opnd0 = N->getOperand(0);
- if (auto CN = dyn_cast<ConstantSDNode>(Opnd0))
- if (CN->isZero())
- return true;
- if (auto CN = dyn_cast<ConstantFPSDNode>(Opnd0))
- if (CN->isZero())
- return true;
+ if (isNullConstant(Opnd0))
+ return true;
+ if (isNullFPConstant(Opnd0))
+ return true;
break;
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f9e141fc893da..388e6f55ac500 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2693,9 +2693,7 @@ static bool isZerosVector(const SDNode *N) {
return false;
auto Opnd0 = N->getOperand(0);
- auto *CINT = dyn_cast<ConstantSDNode>(Opnd0);
- auto *CFP = dyn_cast<ConstantFPSDNode>(Opnd0);
- return (CINT && CINT->isZero()) || (CFP && CFP->isZero());
+ return isNullConstant(Opnd0) || isNullFPConstant(Opnd0);
}
/// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
diff --git a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
index 6929493858972..48e90cd0d09d6 100644
--- a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
@@ -360,6 +360,78 @@ define <vscale x 2 x double> @sel_merge_nx2f64_zero(<vscale x 2 x i1> %p, <vscal
ret <vscale x 2 x double> %sel
}
+define <vscale x 8 x half> @sel_merge_nxv8f16_negative_zero(<vscale x 8 x i1> %p, <vscale x 8 x half> %in) {
+; CHECK-LABEL: sel_merge_nxv8f16_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #32768
+; CHECK-NEXT: mov z1.h, w8
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 8 x half> insertelement (<vscale x 8 x half> undef, half -0.0, i32 0), <vscale x 8 x half> zeroinitializer, <vscale x 8 x i32> zeroinitializer
+%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %vec, <vscale x 8 x half> %in
+ret <vscale x 8 x half> %sel
+}
+
+define <vscale x 4 x half> @sel_merge_nx4f16_negative_zero(<vscale x 4 x i1> %p, <vscale x 4 x half> %in) {
+; CHECK-LABEL: sel_merge_nx4f16_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #32768
+; CHECK-NEXT: mov z1.h, w8
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 4 x half> insertelement (<vscale x 4 x half> undef, half -0.0, i32 0), <vscale x 4 x half> zeroinitializer, <vscale x 4 x i32> zeroinitializer
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> %vec, <vscale x 4 x half> %in
+ret <vscale x 4 x half> %sel
+}
+
+define <vscale x 2 x half> @sel_merge_nx2f16_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x half> %in) {
+; CHECK-LABEL: sel_merge_nx2f16_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #32768
+; CHECK-NEXT: mov z1.h, w8
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 2 x half> insertelement (<vscale x 2 x half> undef, half -0.0, i32 0), <vscale x 2 x half> zeroinitializer, <vscale x 2 x i32> zeroinitializer
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> %vec, <vscale x 2 x half> %in
+ret <vscale x 2 x half> %sel
+}
+
+define <vscale x 4 x float> @sel_merge_nx4f32_negative_zero(<vscale x 4 x i1> %p, <vscale x 4 x float> %in) {
+; CHECK-LABEL: sel_merge_nx4f32_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-2147483648
+; CHECK-NEXT: mov z1.s, w8
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 4 x float> insertelement (<vscale x 4 x float> undef, float -0.0, i32 0), <vscale x 4 x float> zeroinitializer, <vscale x 4 x i32> zeroinitializer
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %vec, <vscale x 4 x float> %in
+ret <vscale x 4 x float> %sel
+}
+
+define <vscale x 2 x float> @sel_merge_nx2f32_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x float> %in) {
+; CHECK-LABEL: sel_merge_nx2f32_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-2147483648
+; CHECK-NEXT: mov z1.s, w8
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 2 x float> insertelement (<vscale x 2 x float> undef, float -0.0, i32 0), <vscale x 2 x float> zeroinitializer, <vscale x 2 x i32> zeroinitializer
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %vec, <vscale x 2 x float> %in
+ret <vscale x 2 x float> %sel
+}
+
+define <vscale x 2 x double> @sel_merge_nx2f64_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x double> %in) {
+; CHECK-LABEL: sel_merge_nx2f64_negative_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-9223372036854775808
+; CHECK-NEXT: mov z1.d, x8
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%vec = shufflevector <vscale x 2 x double> insertelement (<vscale x 2 x double> undef, double -0.0, i32 0), <vscale x 2 x double> zeroinitializer, <vscale x 2 x i32> zeroinitializer
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %vec, <vscale x 2 x double> %in
+ret <vscale x 2 x double> %sel
+}
+
define <vscale x 8 x i16> @sel_merge_16_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {
; CHECK-LABEL: sel_merge_16_shifted:
; CHECK: // %bb.0:
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