[PATCH] D132938: [AMDGPU] Fix crash legalizing G_EXTRACT_VECTOR_ELT with negative index
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 30 06:11:19 PDT 2022
foad created this revision.
Herald added subscribers: kosarev, kerbowa, arphaman, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
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foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
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Fixes https://github.com/llvm/llvm-project/issues/57408
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D132938
Files:
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn -global-isel < %s | FileCheck %s
+
+define void @f() {
+; CHECK-LABEL: f:
+; CHECK: ; %bb.0: ; %BB
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+BB:
+ br label %BB2
+
+BB2: ; preds = %BB
+ br label %BB1
+
+BB1: ; preds = %BB2
+ %B1 = sub <2 x i8> <i8 16, i8 16>, <i8 16, i8 16>
+ %A = alloca i8, align 4, addrspace(5)
+ %L1 = load i8, i8 addrspace(5)* %A, align 1
+ %I = insertelement <2 x i8> %B1, i8 -128, i8 %L1
+ %E1 = extractelement <2 x i8> %I, i1 true
+ store i8 %E1, i8 addrspace(5)* %A, align 1
+ ret void
+}
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2352,7 +2352,7 @@
LLT EltTy = VecTy.getElementType();
assert(EltTy == MRI.getType(Dst));
- if (IdxVal < VecTy.getNumElements()) {
+ if (IdxVal >= 0 && IdxVal < VecTy.getNumElements()) {
auto Unmerge = B.buildUnmerge(EltTy, Vec);
B.buildCopy(Dst, Unmerge.getReg(IdxVal));
} else {
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