[llvm] 72c9f81 - [RISCV][COST] Refactor for costs of integer saturing add/sub
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 29 20:40:24 PDT 2022
Author: liqinweng
Date: 2022-08-30T11:39:55+08:00
New Revision: 72c9f811d899651f63ebcc5b585be176ccc85bfe
URL: https://github.com/llvm/llvm-project/commit/72c9f811d899651f63ebcc5b585be176ccc85bfe
DIFF: https://github.com/llvm/llvm-project/commit/72c9f811d899651f63ebcc5b585be176ccc85bfe.diff
LOG: [RISCV][COST] Refactor for costs of integer saturing add/sub
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D132822
Added:
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index debf8252b10a..01e5aeaae8c4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -445,130 +445,6 @@ static const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::ctpop, MVT::nxv2i64, 21},
{Intrinsic::ctpop, MVT::nxv4i64, 21},
{Intrinsic::ctpop, MVT::nxv8i64, 21},
- {Intrinsic::sadd_sat, MVT::v2i8, 1},
- {Intrinsic::sadd_sat, MVT::v4i8, 1},
- {Intrinsic::sadd_sat, MVT::v8i8, 1},
- {Intrinsic::sadd_sat, MVT::v16i8, 1},
- {Intrinsic::sadd_sat, MVT::nxv2i8, 1},
- {Intrinsic::sadd_sat, MVT::nxv4i8, 1},
- {Intrinsic::sadd_sat, MVT::nxv8i8, 1},
- {Intrinsic::sadd_sat, MVT::nxv16i8, 1},
- {Intrinsic::sadd_sat, MVT::v2i16, 1},
- {Intrinsic::sadd_sat, MVT::v4i16, 1},
- {Intrinsic::sadd_sat, MVT::v8i16, 1},
- {Intrinsic::sadd_sat, MVT::v16i16, 1},
- {Intrinsic::sadd_sat, MVT::nxv2i16, 1},
- {Intrinsic::sadd_sat, MVT::nxv4i16, 1},
- {Intrinsic::sadd_sat, MVT::nxv8i16, 1},
- {Intrinsic::sadd_sat, MVT::nxv16i16, 1},
- {Intrinsic::sadd_sat, MVT::v2i32, 1},
- {Intrinsic::sadd_sat, MVT::v4i32, 1},
- {Intrinsic::sadd_sat, MVT::v8i32, 1},
- {Intrinsic::sadd_sat, MVT::v16i32, 1},
- {Intrinsic::sadd_sat, MVT::nxv2i32, 1},
- {Intrinsic::sadd_sat, MVT::nxv4i32, 1},
- {Intrinsic::sadd_sat, MVT::nxv8i32, 1},
- {Intrinsic::sadd_sat, MVT::nxv16i32, 1},
- {Intrinsic::sadd_sat, MVT::v2i64, 1},
- {Intrinsic::sadd_sat, MVT::v4i64, 1},
- {Intrinsic::sadd_sat, MVT::v8i64, 1},
- {Intrinsic::sadd_sat, MVT::v16i64, 1},
- {Intrinsic::sadd_sat, MVT::nxv2i64, 1},
- {Intrinsic::sadd_sat, MVT::nxv4i64, 1},
- {Intrinsic::sadd_sat, MVT::nxv8i64, 1},
- {Intrinsic::uadd_sat, MVT::v2i8, 1},
- {Intrinsic::uadd_sat, MVT::v4i8, 1},
- {Intrinsic::uadd_sat, MVT::v8i8, 1},
- {Intrinsic::uadd_sat, MVT::v16i8, 1},
- {Intrinsic::uadd_sat, MVT::nxv2i8, 1},
- {Intrinsic::uadd_sat, MVT::nxv4i8, 1},
- {Intrinsic::uadd_sat, MVT::nxv8i8, 1},
- {Intrinsic::uadd_sat, MVT::nxv16i8, 1},
- {Intrinsic::uadd_sat, MVT::v2i16, 1},
- {Intrinsic::uadd_sat, MVT::v4i16, 1},
- {Intrinsic::uadd_sat, MVT::v8i16, 1},
- {Intrinsic::uadd_sat, MVT::v16i16, 1},
- {Intrinsic::uadd_sat, MVT::nxv2i16, 1},
- {Intrinsic::uadd_sat, MVT::nxv4i16, 1},
- {Intrinsic::uadd_sat, MVT::nxv8i16, 1},
- {Intrinsic::uadd_sat, MVT::nxv16i16, 1},
- {Intrinsic::uadd_sat, MVT::v2i32, 1},
- {Intrinsic::uadd_sat, MVT::v4i32, 1},
- {Intrinsic::uadd_sat, MVT::v8i32, 1},
- {Intrinsic::uadd_sat, MVT::v16i32, 1},
- {Intrinsic::uadd_sat, MVT::nxv2i32, 1},
- {Intrinsic::uadd_sat, MVT::nxv4i32, 1},
- {Intrinsic::uadd_sat, MVT::nxv8i32, 1},
- {Intrinsic::uadd_sat, MVT::nxv16i32, 1},
- {Intrinsic::uadd_sat, MVT::v2i64, 1},
- {Intrinsic::uadd_sat, MVT::v4i64, 1},
- {Intrinsic::uadd_sat, MVT::v8i64, 1},
- {Intrinsic::uadd_sat, MVT::v16i64, 1},
- {Intrinsic::uadd_sat, MVT::nxv2i64, 1},
- {Intrinsic::uadd_sat, MVT::nxv4i64, 1},
- {Intrinsic::uadd_sat, MVT::nxv8i64, 1},
- {Intrinsic::usub_sat, MVT::v2i8, 1},
- {Intrinsic::usub_sat, MVT::v4i8, 1},
- {Intrinsic::usub_sat, MVT::v8i8, 1},
- {Intrinsic::usub_sat, MVT::v16i8, 1},
- {Intrinsic::usub_sat, MVT::nxv2i8, 1},
- {Intrinsic::usub_sat, MVT::nxv4i8, 1},
- {Intrinsic::usub_sat, MVT::nxv8i8, 1},
- {Intrinsic::usub_sat, MVT::nxv16i8, 1},
- {Intrinsic::usub_sat, MVT::v2i16, 1},
- {Intrinsic::usub_sat, MVT::v4i16, 1},
- {Intrinsic::usub_sat, MVT::v8i16, 1},
- {Intrinsic::usub_sat, MVT::v16i16, 1},
- {Intrinsic::usub_sat, MVT::nxv2i16, 1},
- {Intrinsic::usub_sat, MVT::nxv4i16, 1},
- {Intrinsic::usub_sat, MVT::nxv8i16, 1},
- {Intrinsic::usub_sat, MVT::nxv16i16, 1},
- {Intrinsic::usub_sat, MVT::v2i32, 1},
- {Intrinsic::usub_sat, MVT::v4i32, 1},
- {Intrinsic::usub_sat, MVT::v8i32, 1},
- {Intrinsic::usub_sat, MVT::v16i32, 1},
- {Intrinsic::usub_sat, MVT::nxv2i32, 1},
- {Intrinsic::usub_sat, MVT::nxv4i32, 1},
- {Intrinsic::usub_sat, MVT::nxv8i32, 1},
- {Intrinsic::usub_sat, MVT::nxv16i32, 1},
- {Intrinsic::usub_sat, MVT::v2i64, 1},
- {Intrinsic::usub_sat, MVT::v4i64, 1},
- {Intrinsic::usub_sat, MVT::v8i64, 1},
- {Intrinsic::usub_sat, MVT::v16i64, 1},
- {Intrinsic::usub_sat, MVT::nxv2i64, 1},
- {Intrinsic::usub_sat, MVT::nxv4i64, 1},
- {Intrinsic::usub_sat, MVT::nxv8i64, 1},
- {Intrinsic::ssub_sat, MVT::v2i8, 1},
- {Intrinsic::ssub_sat, MVT::v4i8, 1},
- {Intrinsic::ssub_sat, MVT::v8i8, 1},
- {Intrinsic::ssub_sat, MVT::v16i8, 1},
- {Intrinsic::ssub_sat, MVT::nxv2i8, 1},
- {Intrinsic::ssub_sat, MVT::nxv4i8, 1},
- {Intrinsic::ssub_sat, MVT::nxv8i8, 1},
- {Intrinsic::ssub_sat, MVT::nxv16i8, 1},
- {Intrinsic::ssub_sat, MVT::v2i16, 1},
- {Intrinsic::ssub_sat, MVT::v4i16, 1},
- {Intrinsic::ssub_sat, MVT::v8i16, 1},
- {Intrinsic::ssub_sat, MVT::v16i16, 1},
- {Intrinsic::ssub_sat, MVT::nxv2i16, 1},
- {Intrinsic::ssub_sat, MVT::nxv4i16, 1},
- {Intrinsic::ssub_sat, MVT::nxv8i16, 1},
- {Intrinsic::ssub_sat, MVT::nxv16i16, 1},
- {Intrinsic::ssub_sat, MVT::v2i32, 1},
- {Intrinsic::ssub_sat, MVT::v4i32, 1},
- {Intrinsic::ssub_sat, MVT::v8i32, 1},
- {Intrinsic::ssub_sat, MVT::v16i32, 1},
- {Intrinsic::ssub_sat, MVT::nxv2i32, 1},
- {Intrinsic::ssub_sat, MVT::nxv4i32, 1},
- {Intrinsic::ssub_sat, MVT::nxv8i32, 1},
- {Intrinsic::ssub_sat, MVT::nxv16i32, 1},
- {Intrinsic::ssub_sat, MVT::v2i64, 1},
- {Intrinsic::ssub_sat, MVT::v4i64, 1},
- {Intrinsic::ssub_sat, MVT::v8i64, 1},
- {Intrinsic::ssub_sat, MVT::v16i64, 1},
- {Intrinsic::ssub_sat, MVT::nxv2i64, 1},
- {Intrinsic::ssub_sat, MVT::nxv4i64, 1},
- {Intrinsic::ssub_sat, MVT::nxv8i64, 1},
};
InstructionCost
@@ -586,6 +462,15 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
return LT.first;
break;
}
+ case Intrinsic::sadd_sat:
+ case Intrinsic::ssub_sat:
+ case Intrinsic::uadd_sat:
+ case Intrinsic::usub_sat: {
+ auto LT = getTypeLegalizationCost(RetTy);
+ if (ST->hasVInstructions() && LT.second.isVector())
+ return LT.first;
+ break;
+ }
// TODO: add more intrinsic
case Intrinsic::experimental_stepvector: {
unsigned Cost = 1; // vid
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