[llvm] 7c17b0a - [RISCV] Add test case for missed opportunity to use ANDI.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-29T14:02:07-07:00
New Revision: 7c17b0afb10590b7c0fd2e63f9a82e1c49c3fec3

URL: https://github.com/llvm/llvm-project/commit/7c17b0afb10590b7c0fd2e63f9a82e1c49c3fec3
DIFF: https://github.com/llvm/llvm-project/commit/7c17b0afb10590b7c0fd2e63f9a82e1c49c3fec3.diff

LOG: [RISCV] Add test case for missed opportunity to use ANDI.

Immediate was messed up by SimplfyDemandedBits.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
index ca9f43dd7ad7..b6f64daaf442 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -98,3 +98,26 @@ define void @xor_signbit(ptr nocapture noundef %0) {
   store i32 %3, ptr %0, align 4
   ret void
 }
+
+; Type legalization inserts a sext_inreg after the sub. This causes the
+; constant for the AND to be turned into 0xfffffff8. Then SimplifyDemandedBits
+; removes the sext_inreg from the path to the store. This prevents
+; TargetShrinkDemandedConstant from being able to restore the lost upper bits
+; from the and mask to allow andi. ISel is able to recover the lost sext_inreg
+; using hasAllWUsers.
+; FIXME: Use hasAllWUers to recover the ANDI.
+define signext i32 @andi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: andi_sub_cse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a3, 1
+; CHECK-NEXT:    slli a3, a3, 32
+; CHECK-NEXT:    addi a3, a3, -8
+; CHECK-NEXT:    and a0, a0, a3
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    sw a0, 0(a2)
+; CHECK-NEXT:    ret
+  %4 = and i32 %0, -8
+  %5 = sub i32 %4, %1
+  store i32 %5, ptr %2, align 4
+  ret i32 %5
+}