[llvm] 1a1c59f - [RISCV][NFC] Refactor fadd test to match the code.

[via llvm-commits]

Author: jacquesguan
Date: 2022-08-29T10:45:29+08:00
New Revision: 1a1c59f9958609438c13af73444061d85caa749c

URL: https://github.com/llvm/llvm-project/commit/1a1c59f9958609438c13af73444061d85caa749c
DIFF: https://github.com/llvm/llvm-project/commit/1a1c59f9958609438c13af73444061d85caa749c.diff

LOG: [RISCV][NFC] Refactor fadd test to match the code.

Change fadd test case in D122563 to match the fold base case.

Differential Revision: https://reviews.llvm.org/D132722

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
index a4d98e73cf5e..698ad1481ef1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
@@ -256,6 +256,21 @@ entry:
   ret float %rdx
 }
 
+define float @reduce_fadd2(float %x, <4 x float> %v) {
+; CHECK-LABEL: reduce_fadd2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vfredusum.vs v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+entry:
+  %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.0, <4 x float> %v)
+  %res = fadd fast float %rdx, %x
+  ret float %res
+}
+
 define float @reduce_fmax(float %x, <4 x float> %v) {
 ; CHECK-LABEL: reduce_fmax:
 ; CHECK:       # %bb.0: # %entry