[llvm] 2833760 - [Target] Qualify auto in range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 28 17:35:40 PDT 2022
Author: Kazu Hirata
Date: 2022-08-28T17:35:09-07:00
New Revision: 2833760c57a52bb55a4ffc7efce6a2bf37a8d5fc
URL: https://github.com/llvm/llvm-project/commit/2833760c57a52bb55a4ffc7efce6a2bf37a8d5fc
DIFF: https://github.com/llvm/llvm-project/commit/2833760c57a52bb55a4ffc7efce6a2bf37a8d5fc.diff
LOG: [Target] Qualify auto in range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
llvm/lib/Target/AArch64/AArch64StackTagging.cpp
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
llvm/lib/Target/ARM/ARMParallelDSP.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/MVETailPredication.cpp
llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
llvm/lib/Target/BPF/BPFPreserveDIType.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/lib/Target/Hexagon/RDFCopy.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86OptimizeLEAs.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
index 64f0bb63762de..1c20e24e41d7e 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
@@ -153,7 +153,7 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
return nullptr;
// Since we may modify cmp of this MBB, make sure NZCV does not live out.
- for (auto SuccBB : MBB->successors())
+ for (auto *SuccBB : MBB->successors())
if (SuccBB->isLiveIn(AArch64::NZCV))
return nullptr;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 6e358c2193e82..b933b12e64983 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -924,7 +924,7 @@ bool AArch64DAGToDAGISel::SelectArithUXTXRegister(SDValue N, SDValue &Reg,
/// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
/// leads to duplicated ADRP instructions.
static bool isWorthFoldingADDlow(SDValue N) {
- for (auto Use : N->uses()) {
+ for (auto *Use : N->uses()) {
if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
Use->getOpcode() != ISD::ATOMIC_LOAD &&
Use->getOpcode() != ISD::ATOMIC_STORE)
diff --git a/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp b/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
index 841275cfe82f6..85b32f9df0e1f 100644
--- a/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
@@ -681,7 +681,7 @@ bool AArch64SpeculationHardening::runOnMachineFunction(MachineFunction &MF) {
EntryBlocks.push_back(&MF.front());
for (const LandingPadInfo &LPI : MF.getLandingPads())
EntryBlocks.push_back(LPI.LandingPadBlock);
- for (auto Entry : EntryBlocks)
+ for (auto *Entry : EntryBlocks)
insertSPToRegTaintPropagation(
*Entry, Entry->SkipPHIsLabelsAndDebug(Entry->begin()));
diff --git a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
index 24816bc9e9bd5..072b29fb3dfa3 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
@@ -598,7 +598,7 @@ bool AArch64StackTagging::runOnFunction(Function &Fn) {
}
// Fixup debug intrinsics to point to the new alloca.
- for (auto DVI : Info.DbgVariableIntrinsics)
+ for (auto *DVI : Info.DbgVariableIntrinsics)
DVI->replaceVariableLocationOp(OldAI, Info.AI);
}
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 6c8952414388f..879dcbf6e97dc 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1070,7 +1070,7 @@ void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
: MCDR_DataRegionJT16);
- for (auto MBB : JTBBs) {
+ for (auto *MBB : JTBBs) {
const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
OutContext);
// Otherwise it's an offset from the dispatch instruction. Construct an
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 2ca5df0182b6a..4142eebe11881 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6899,7 +6899,7 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
// Learn whether the last use/def of each cross-iteration register is a use or
// def. If it is a def, RegisterPressure will implicitly increase max pressure
// and we do not have to add the pressure.
- for (auto SU : ProposedSchedule)
+ for (auto *SU : ProposedSchedule)
for (ConstMIBundleOperands OperI(*SU->getInstr()); OperI.isValid();
++OperI) {
auto MO = *OperI;
@@ -6928,7 +6928,7 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
bumpCrossIterationPressure(RPTracker, CrossIterationNeeds);
- for (auto SU : ProposedSchedule) {
+ for (auto *SU : ProposedSchedule) {
MachineBasicBlock::const_iterator CurInstI = SU->getInstr();
RPTracker.setPos(std::next(CurInstI));
RPTracker.recede();
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9da2cf2a9f94b..999f7393ceee1 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13706,7 +13706,7 @@ static SDValue PerformSHLSimplify(SDNode *N,
return SDValue();
// Check that all the users could perform the shl themselves.
- for (auto U : N->uses()) {
+ for (auto *U : N->uses()) {
switch(U->getOpcode()) {
default:
return SDValue();
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index aa739db44da2c..7abde69be25a2 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1201,7 +1201,7 @@ static bool ValidateMVEStore(MachineInstr *MI, MachineLoop *ML) {
}
if (LookAtSuccessors) {
- for (auto Succ : BB->successors()) {
+ for (auto *Succ : BB->successors()) {
if (!Visited.contains(Succ) && !is_contained(Frontier, Succ))
Frontier.push_back(Succ);
}
@@ -1317,7 +1317,7 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
BBUtils->adjustBBOffsetsAfter(&MF->front());
bool Changed = false;
- for (auto ML : *MLI) {
+ for (auto *ML : *MLI) {
if (ML->isOutermost())
Changed |= ProcessLoop(ML);
}
diff --git a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
index 348895da713f6..61d3312bf2532 100644
--- a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
+++ b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
@@ -89,7 +89,7 @@ bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
}
bool Changed = false;
// Remove the tagged DMB
- for (auto MI : ToRemove) {
+ for (auto *MI : ToRemove) {
MI->eraseFromParent();
++NumDMBsRemoved;
Changed = true;
diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
index 2f65423b40970..d9b90af4fa996 100644
--- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
@@ -367,8 +367,8 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
// Record any writes that may alias a load.
const auto Size = LocationSize::beforeOrAfterPointer();
- for (auto Write : Writes) {
- for (auto Read : Loads) {
+ for (auto *Write : Writes) {
+ for (auto *Read : Loads) {
MemoryLocation ReadLoc =
MemoryLocation(Read->getPointerOperand(), Size);
@@ -389,7 +389,7 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
if (RAWDeps.count(Dominated)) {
InstSet &WritesBefore = RAWDeps[Dominated];
- for (auto Before : WritesBefore) {
+ for (auto *Before : WritesBefore) {
// We can't move the second load backward, past a write, to merge
// with the first load.
if (Dominator->comesBefore(Before))
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index f5b99d0e23e68..1d6e29510950c 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -2066,7 +2066,7 @@ bool ARMTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
};
// Visit inner loops.
- for (auto Inner : *L)
+ for (auto *Inner : *L)
if (!ScanLoop(Inner))
return false;
diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp
index 0e6960bce32b5..e1e18347cfd18 100644
--- a/llvm/lib/Target/ARM/MVETailPredication.cpp
+++ b/llvm/lib/Target/ARM/MVETailPredication.cpp
@@ -418,7 +418,7 @@ bool MVETailPredication::TryConvertActiveLaneMask(Value *TripCount) {
// Remove dead instructions and now dead phis.
for (auto *II : ActiveLaneMasks)
RecursivelyDeleteTriviallyDeadInstructions(II);
- for (auto I : L->blocks())
+ for (auto *I : L->blocks())
DeleteDeadPHIs(I);
return true;
}
diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
index 9aad9375d913a..1dedfb6294690 100644
--- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
+++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
@@ -438,7 +438,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
void BPFAbstractMemberAccess::replaceWithGEP(std::vector<CallInst *> &CallList,
uint32_t DimensionIndex,
uint32_t GEPIndex) {
- for (auto Call : CallList) {
+ for (auto *Call : CallList) {
uint32_t Dimension = 1;
if (DimensionIndex > 0)
Dimension = getConstant(Call->getArgOperand(DimensionIndex));
@@ -491,7 +491,7 @@ bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) {
// addr = GEP(base, 0, gep_index)
replaceWithGEP(PreserveArrayIndexCalls, 1, 2);
replaceWithGEP(PreserveStructIndexCalls, 0, 1);
- for (auto Call : PreserveUnionIndexCalls) {
+ for (auto *Call : PreserveUnionIndexCalls) {
Call->replaceAllUsesWith(Call->getArgOperand(0));
Call->eraseFromParent();
}
diff --git a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
index 8c58aae5b618c..58d18e66a6aa2 100644
--- a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
+++ b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
@@ -70,7 +70,7 @@ static bool BPFPreserveDITypeImpl(Function &F) {
std::string BaseName = "llvm.btf_type_id.";
static int Count = 0;
- for (auto Call : PreserveDITypeCalls) {
+ for (auto *Call : PreserveDITypeCalls) {
const ConstantInt *Flag = dyn_cast<ConstantInt>(Call->getArgOperand(1));
assert(Flag);
uint64_t FlagValue = Flag->getValue().getZExtValue();
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d942276ddc23c..5b12fff8e9a0a 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1026,7 +1026,7 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
for (MachineInstr &MI : llvm::reverse(*B))
Instrs.push_back(&MI);
- for (auto MI : Instrs) {
+ for (auto *MI : Instrs) {
unsigned Opc = MI->getOpcode();
// Do not touch lifetime markers. This is why the target-independent DCE
// cannot be used.
@@ -1755,7 +1755,7 @@ bool CopyPropagation::processBlock(MachineBasicBlock &B, const RegisterSet&) {
Instrs.push_back(&MI);
bool Changed = false;
- for (auto I : Instrs) {
+ for (auto *I : Instrs) {
unsigned Opc = I->getOpcode();
if (!CopyPropagation::isCopyReg(Opc, true))
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
index 2fe2e032714a6..5ad749074a8e2 100644
--- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -1230,7 +1230,7 @@ void HexagonCommonGEP::removeDeadCode() {
for (unsigned i = 0; i < BO.size(); ++i) {
BasicBlock *B = cast<BasicBlock>(BO[i]);
- for (auto DTN : children<DomTreeNode*>(DT->getNode(B)))
+ for (auto *DTN : children<DomTreeNode *>(DT->getNode(B)))
BO.push_back(DTN->getBlock());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index dc5b674424c89..f630bcba379fc 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -625,7 +625,7 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
if (!DoInsertAtI1 && DbgMItoMove.size() != 0) {
// Insert debug instructions at the new location before I2.
MachineBasicBlock *BB = InsertPt->getParent();
- for (auto NewMI : DbgMItoMove) {
+ for (auto *NewMI : DbgMItoMove) {
// If iterator MI is pointing to DEBUG_VAL, make sure
// MI now points to next relevant instruction.
if (NewMI == MI)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 234c2080b027d..e744a52162e24 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -620,7 +620,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
if (MI.getOpcode() == Hexagon::PS_alloca)
AdjustRegs.push_back(&MI);
- for (auto MI : AdjustRegs) {
+ for (auto *MI : AdjustRegs) {
assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
expandAlloca(MI, HII, SP, MaxCF);
MI->eraseFromParent();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 29f6582c65f45..c7d4b721f8a65 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -984,7 +984,7 @@ static bool isMemOPCandidate(SDNode *I, SDNode *U) {
void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
- for (auto I : Nodes) {
+ for (auto *I : Nodes) {
if (I->getOpcode() != ISD::OR)
continue;
@@ -1032,7 +1032,7 @@ void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
- for (auto I : Nodes) {
+ for (auto *I : Nodes) {
if (I->getOpcode() != ISD::STORE)
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index ee92383a6836a..74cd4ce3e309f 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1800,7 +1800,7 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
return true;
// If any of the block's successors is a landing pad, this could be a
// throwing call.
- for (auto I : MBB->successors())
+ for (auto *I : MBB->successors())
if (I->isEHPad())
return true;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index 97a4524386805..4811958409d26 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -1137,7 +1137,7 @@ bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In,
auto *BB = cast<Instruction>(Out)->getParent();
bool HadPhi = false;
- for (auto U : Out->users()) {
+ for (auto *U : Out->users()) {
auto *I = dyn_cast<Instruction>(&*U);
if (I == nullptr || I->getParent() != BB)
continue;
@@ -2346,7 +2346,7 @@ bool HexagonLoopIdiomRecognize::coverLoop(Loop *L,
continue;
if (!Worklist.count(&In) && In.mayHaveSideEffects())
return false;
- for (auto K : In.users()) {
+ for (auto *K : In.users()) {
Instruction *UseI = dyn_cast<Instruction>(K);
if (!UseI)
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index b816a7d8d495e..aa31762a96960 100644
--- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -882,7 +882,7 @@ bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
Changed |= processBlock(BA);
- for (auto MI : Deleted)
+ for (auto *MI : Deleted)
MI->eraseFromParent();
if (Changed) {
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 2862ad2d2097d..2e1a8c39887e2 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -1150,7 +1150,7 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
}
MISet Erase;
- for (auto MI : SplitIns) {
+ for (auto *MI : SplitIns) {
if (isFixedInstr(MI)) {
collapseRegPairs(MI, PairMap);
} else {
@@ -1169,11 +1169,11 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
U != W; ++U)
Uses.insert(U->getParent());
- for (auto M : Uses)
+ for (auto *M : Uses)
replaceSubregUses(M, PairMap);
}
- for (auto MI : Erase) {
+ for (auto *MI : Erase) {
MachineBasicBlock *B = MI->getParent();
B->erase(MI);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
index 2c5c64cfcfc65..a647e699a8f07 100644
--- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
@@ -174,7 +174,7 @@ bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
- for (auto SI : Stores) {
+ for (auto *SI : Stores) {
const MachineMemOperand &SMO = getStoreTarget(SI);
if (!SMO.getValue())
return true;
@@ -490,7 +490,7 @@ bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) {
// Create a set of all instructions in OG (for quick lookup).
SmallPtrSet<MachineInstr*, 4> InstrSet;
- for (auto I : OG)
+ for (auto *I : OG)
InstrSet.insert(I);
// Traverse the block, until we hit an instruction from OG.
@@ -514,7 +514,7 @@ bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) {
else
AtBBStart = true;
- for (auto I : OG)
+ for (auto *I : OG)
I->eraseFromParent();
if (!AtBBStart)
@@ -522,7 +522,7 @@ bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) {
else
InsertAt = MBB->begin();
- for (auto I : NG)
+ for (auto *I : NG)
MBB->insert(InsertAt, I);
return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 54d33a4113e70..df4b14b70f255 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -383,7 +383,7 @@ bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI,
void HexagonPacketizerList::cleanUpDotCur() {
MachineInstr *MI = nullptr;
- for (auto BI : CurrentPacketMIs) {
+ for (auto *BI : CurrentPacketMIs) {
LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
if (HII->isDotCurInst(*BI)) {
MI = BI;
@@ -440,7 +440,7 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
// Check for existing uses of a vector register within the packet which
// would be affected by converting a vector load into .cur formt.
- for (auto BI : CurrentPacketMIs) {
+ for (auto *BI : CurrentPacketMIs) {
LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
return false;
@@ -668,7 +668,7 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
// New-value stores are of class NV (slot 0), dual stores require class ST
// in slot 0 (PRM 5.5).
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
SUnit *PacketSU = MIToSUnit.find(I)->second;
if (PacketSU->getInstr()->mayStore())
return false;
@@ -754,7 +754,7 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
unsigned StartCheck = 0;
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
SUnit *TempSU = MIToSUnit.find(I)->second;
MachineInstr &TempMI = *TempSU->getInstr();
@@ -920,7 +920,7 @@ bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
unsigned DepReg) {
SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
// We only care for dependencies to predicated instructions
if (!HII->isPredicated(*I))
continue;
@@ -990,7 +990,7 @@ bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
// Analyze relationships between all existing members of the packet.
// Look for Anti dependecy on the same predicate reg as used in the
// candidate.
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
// Scheduling Unit for current insn in the packet.
SUnit *PacketSU = MIToSUnit.find(I)->second;
@@ -1690,7 +1690,7 @@ bool HexagonPacketizerList::foundLSInPacket() {
bool FoundLoad = false;
bool FoundStore = false;
- for (auto MJ : CurrentPacketMIs) {
+ for (auto *MJ : CurrentPacketMIs) {
unsigned Opc = MJ->getOpcode();
if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
continue;
@@ -1915,7 +1915,7 @@ unsigned int HexagonPacketizerList::calcStall(const MachineInstr &I) {
// }
// Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
- for (auto J : CurrentPacketMIs) {
+ for (auto *J : CurrentPacketMIs) {
SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds)
if (Pred.getSUnit() == SUJ)
@@ -1926,7 +1926,7 @@ unsigned int HexagonPacketizerList::calcStall(const MachineInstr &I) {
// Check if the latency is greater than one between this instruction and any
// instruction in the previous packet.
- for (auto J : OldPacketMIs) {
+ for (auto *J : OldPacketMIs) {
SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds)
if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 27a1830f05234..08ab3dbfee4a3 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -713,7 +713,7 @@ class HexagonAsmBackend : public MCAsmBackend {
void finishLayout(MCAssembler const &Asm,
MCAsmLayout &Layout) const override {
- for (auto I : Layout.getSectionOrder()) {
+ for (auto *I : Layout.getSectionOrder()) {
auto &Fragments = I->getFragmentList();
for (auto &J : Fragments) {
switch (J.getKind()) {
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp
index 34d58f0a7a230..cb31ec0683257 100644
--- a/llvm/lib/Target/Hexagon/RDFCopy.cpp
+++ b/llvm/lib/Target/Hexagon/RDFCopy.cpp
@@ -79,7 +79,7 @@ bool CopyPropagation::scanBlock(MachineBasicBlock *B) {
}
MachineDomTreeNode *N = MDT.getNode(B);
- for (auto I : *N)
+ for (auto *I : *N)
Changed |= scanBlock(I->getBlock());
return Changed;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 48fa387e563ab..9212e06fcfd35 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -612,7 +612,7 @@ bool NVPTXDAGToDAGISel::tryEXTRACT_VECTOR_ELEMENT(SDNode *N) {
// Find and record all uses of this vector that extract element 0 or 1.
SmallVector<SDNode *, 4> E0, E1;
- for (auto U : Vector.getNode()->uses()) {
+ for (auto *U : Vector.getNode()->uses()) {
if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
continue;
if (U->getOperand(0) != Vector)
diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
index f0c6e83e7e772..15185899e5507 100644
--- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -99,7 +99,7 @@ bool PPCCTRLoops::runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
MRI = &MF.getRegInfo();
- for (auto ML : MLI) {
+ for (auto *ML : MLI) {
if (ML->isOutermost())
Changed |= processLoop(ML);
}
diff --git a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
index 770b17b162a37..302b8acf83f9d 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
@@ -714,7 +714,7 @@ PPCLoopInstrFormPrep::rewriteForBase(Loop *L, const SCEVAddRecExpr *BasePtrSCEV,
// Note that LoopPredecessor might occur in the predecessor list multiple
// times, and we need to add it the right number of times.
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI != LoopPredecessor)
continue;
@@ -729,7 +729,7 @@ PPCLoopInstrFormPrep::rewriteForBase(Loop *L, const SCEVAddRecExpr *BasePtrSCEV,
I8Ty, NewPHI, IncNode, getInstrName(BaseMemI, GEPNodeIncNameSuffix),
InsPoint);
cast<GetElementPtrInst>(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr));
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI == LoopPredecessor)
continue;
@@ -744,7 +744,7 @@ PPCLoopInstrFormPrep::rewriteForBase(Loop *L, const SCEVAddRecExpr *BasePtrSCEV,
} else {
// Note that LoopPredecessor might occur in the predecessor list multiple
// times, and we need to make sure no more incoming value for them in PHI.
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI == LoopPredecessor)
continue;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d545b39effaa6..0fd0d4c9f530a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1919,7 +1919,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
// Is this ADD instruction only used as the base pointer of scalar loads and
// stores?
static bool isWorthFoldingAdd(SDValue Add) {
- for (auto Use : Add->uses()) {
+ for (auto *Use : Add->uses()) {
if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
Use->getOpcode() != ISD::ATOMIC_LOAD &&
Use->getOpcode() != ISD::ATOMIC_STORE)
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 319967a8ad75b..4f6024ba79075 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -456,7 +456,7 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
}
bool MadeChange = false;
- for (auto MI : SExtWRemovalCands) {
+ for (auto *MI : SExtWRemovalCands) {
SmallPtrSet<MachineInstr *, 4> FixableDef;
Register SrcReg = MI->getOperand(1).getReg();
MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
@@ -478,7 +478,7 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
BuildMI(MBB, Fixable, DL, ST.getInstrInfo()->get(Code));
for (auto Op : Fixable->operands())
Replacement.add(Op);
- for (auto Op : Fixable->memoperands())
+ for (auto *Op : Fixable->memoperands())
Replacement.addMemOperand(Op);
LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 32880d7305ed1..56d72aba45dbf 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -7557,7 +7557,7 @@ static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
// destination registers, and the registers that went into the PHI.
DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
- for (auto MI : Selects) {
+ for (auto *MI : Selects) {
Register DestReg = MI->getOperand(0).getReg();
Register TrueReg = MI->getOperand(1).getReg();
Register FalseReg = MI->getOperand(2).getReg();
@@ -7620,7 +7620,7 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI,
NextMIIt->usesCustomInsertionHook())
break;
bool User = false;
- for (auto SelMI : Selects)
+ for (auto *SelMI : Selects)
if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
User = true;
break;
@@ -7668,11 +7668,11 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI,
// ...
MBB = JoinMBB;
createPHIsForSelects(Selects, StartMBB, FalseMBB, MBB);
- for (auto SelMI : Selects)
+ for (auto *SelMI : Selects)
SelMI->eraseFromParent();
MachineBasicBlock::iterator InsertPos = MBB->getFirstNonPHI();
- for (auto DbgMI : DbgValues)
+ for (auto *DbgMI : DbgValues)
MBB->splice(InsertPos, StartMBB, DbgMI);
return JoinMBB;
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index b105c3499a8de..75e3c9741d70c 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -2620,7 +2620,7 @@ VETargetLowering::emitSjLjDispatchBlock(MachineInstr &MI,
SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(),
MBB->succ_rend());
// FIXME: Avoid quadratic complexity.
- for (auto MBBS : Successors) {
+ for (auto *MBBS : Successors) {
if (MBBS->isEHPad()) {
MBB->removeSuccessor(MBBS);
MBBLPads.push_back(MBBS);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
index 2257d1562513b..497ab54406789 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
@@ -235,7 +235,7 @@ static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI,
// any blocks deferred because the header didn't dominate them.
for (Entry &E : Entries)
if (E.TheRegion->contains(MBB) && --E.NumBlocksLeft == 0)
- for (auto DeferredBlock : E.Deferred)
+ for (auto *DeferredBlock : E.Deferred)
Ready.push(DeferredBlock);
while (!Entries.empty() && Entries.back().NumBlocksLeft == 0)
Entries.pop_back();
@@ -348,14 +348,14 @@ static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI,
if (Region->isLoop()) {
// Loop header. The loop predecessor should be sorted above, and the
// other predecessors should be backedges below.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(
(Pred->getNumber() < MBB.getNumber() || Region->contains(Pred)) &&
"Loop header predecessors must be loop predecessors or "
"backedges");
} else {
// Exception header. All predecessors should be sorted above.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(Pred->getNumber() < MBB.getNumber() &&
"Non-loop-header predecessors should be topologically sorted");
}
@@ -364,7 +364,7 @@ static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI,
} else {
// Not a region header. All predecessors should be sorted above.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(Pred->getNumber() < MBB.getNumber() &&
"Non-loop-header predecessors should be topologically sorted");
assert(OnStack.count(SRI.getRegionFor(&MBB)) &&
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
index 81fe5395a6def..7e63b6b976321 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
@@ -80,7 +80,7 @@ void WebAssemblyExceptionInfo::recalculate(
const MachineDominanceFrontier &MDF) {
// Postorder traversal of the dominator tree.
SmallVector<std::unique_ptr<WebAssemblyException>, 8> Exceptions;
- for (auto DomNode : post_order(&MDT)) {
+ for (auto *DomNode : post_order(&MDT)) {
MachineBasicBlock *EHPad = DomNode->getBlock();
if (!EHPad->isEHPad())
continue;
@@ -238,7 +238,7 @@ void WebAssemblyExceptionInfo::recalculate(
}
// Add BBs to exceptions' block vector
- for (auto DomNode : post_order(&MDT)) {
+ for (auto *DomNode : post_order(&MDT)) {
MachineBasicBlock *MBB = DomNode->getBlock();
WebAssemblyException *WE = getExceptionFor(MBB);
for (; WE; WE = WE->getParentException())
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
index 83e71d731bfa4..6c46673c36bf0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
@@ -343,7 +343,7 @@ void WebAssemblyFixIrreducibleControlFlow::makeSingleEntryLoop(
BlockVector SortedEntries = getSortedEntries(Entries);
#ifndef NDEBUG
- for (auto Block : SortedEntries)
+ for (auto *Block : SortedEntries)
assert(Block->getNumber() != -1);
if (SortedEntries.size() > 1) {
for (auto I = SortedEntries.begin(), E = SortedEntries.end() - 1; I != E;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 2c60b0c223a4f..7ace0ad5ce630 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1855,7 +1855,7 @@ SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
// Add an operand for each case.
- for (auto MBB : MBBs)
+ for (auto *MBB : MBBs)
Ops.push_back(DAG.getBasicBlock(MBB));
// Add the first MBB as a dummy default target for now. This will be replaced
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 369c7d3d65045..0c7f375141ff7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36255,7 +36255,7 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(),
MBB->succ_rend());
// FIXME: Avoid quadratic complexity.
- for (auto MBBS : Successors) {
+ for (auto *MBBS : Successors) {
if (MBBS->isEHPad()) {
MBB->removeSuccessor(MBBS);
MBBLPads.push_back(MBBS);
diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
index d0562214a025f..780a0223b3409 100644
--- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
+++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
@@ -349,7 +349,7 @@ bool X86OptimizeLEAPass::chooseBestLEA(
BestLEA = nullptr;
// Loop over all LEA instructions.
- for (auto DefMI : List) {
+ for (auto *DefMI : List) {
// Get new address displacement.
int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);
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