[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:19
   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
-                             HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
-                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
-                             HasVInstructions];
+                             HasStdExtZcb, HasStdExtZknd, HasStdExtZkne,
+                             HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
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VincentWu wrote:
> craig.topper wrote:
> > If we put the write Sched information to match the uncompressed forms, is this still needed?
> Sorry, could you explain what is "uncompressed forms"? and where it is?
Every compressed instruction in Zcb has an equivalent instruction with a 32-bit encoding. Both instructions should have the same scheduling information.


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  https://reviews.llvm.org/D131141/new/

https://reviews.llvm.org/D131141