[llvm] 0636aec - [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Alexey Baturo via llvm-commits]

Author: Alexey Baturo
Date: 2022-08-28T18:05:43+03:00
New Revision: 0636aec3305ebc9a8ada43cd536615e4ea107be3

URL: https://github.com/llvm/llvm-project/commit/0636aec3305ebc9a8ada43cd536615e4ea107be3
DIFF: https://github.com/llvm/llvm-project/commit/0636aec3305ebc9a8ada43cd536615e4ea107be3.diff

LOG: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D131340

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9b5154d1264e1..9b536e824b818 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1666,6 +1666,13 @@ def : Pat<(trap), (UNIMP)>;
 // debugger if possible.
 def : Pat<(debugtrap), (EBREAK)>;
 
+let Predicates = [IsRV64], Uses = [X5],
+    Defs = [X1, X6, X7, X28, X29, X30, X31] in
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES 
+  : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
+           [(int_hwasan_check_memaccess_shortgranules X5, GPRJALR:$ptr,
+                                                      (i32 timm:$accessinfo))]>;
+
 /// Simple optimization
 def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),