[PATCH] D132798: [RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This builds on D132771 <https://reviews.llvm.org/D132771> to invert (setlt 0, X) to (setlt X, 1) and
vice versa.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132798

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/setcc-logic.ll

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