[llvm] 7abf233 - [InstCombine] allow poison (undef) element in vector signbit transforms

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-08-27T11:57:05-04:00
New Revision: 7abf233f44b959520ed09e56638e89898810f25e

URL: https://github.com/llvm/llvm-project/commit/7abf233f44b959520ed09e56638e89898810f25e
DIFF: https://github.com/llvm/llvm-project/commit/7abf233f44b959520ed09e56638e89898810f25e.diff

LOG: [InstCombine] allow poison (undef) element in vector signbit transforms

If the shift constant has undefined lanes, we can assume those
are the same as the defined lanes in these transforms:
https://alive2.llvm.org/ce/z/t6TTJ2

Replace undef with poison in the test while here to support
the transition away from undef.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 1a6ef5abb986..ac6c47afdd94 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2246,15 +2246,16 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
 
   // (iN X s>> (N-1)) & Y --> (X s< 0) ? Y : 0
   unsigned FullShift = Ty->getScalarSizeInBits() - 1;
-  if (match(&I, m_c_And(m_OneUse(m_AShr(m_Value(X), m_SpecificInt(FullShift))),
+  if (match(&I, m_c_And(m_OneUse(m_AShr(m_Value(X),
+                                        m_SpecificIntAllowUndef(FullShift))),
                         m_Value(Y)))) {
     Value *IsNeg = Builder.CreateIsNeg(X, "isneg");
     return SelectInst::Create(IsNeg, Y, ConstantInt::getNullValue(Ty));
   }
   // If there's a 'not' of the shifted value, swap the select operands:
   // ~(iN X s>> (N-1)) & Y --> (X s< 0) ? 0 : Y
-  if (match(&I, m_c_And(m_OneUse(m_Not(
-                            m_AShr(m_Value(X), m_SpecificInt(FullShift)))),
+  if (match(&I, m_c_And(m_OneUse(m_Not(m_AShr(
+                            m_Value(X), m_SpecificIntAllowUndef(FullShift)))),
                         m_Value(Y)))) {
     Value *IsNeg = Builder.CreateIsNeg(X, "isneg");
     return SelectInst::Create(IsNeg, ConstantInt::getNullValue(Ty), Y);

diff  --git a/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
index 7a33aec9b0a8..38aff4bc5357 100644
--- a/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
@@ -186,15 +186,14 @@ define i32 @sub_ashr_and_i32_no_nuw_nsw(i32 %x, i32 %y) {
   ret i32 %and
 }
 
-define <4 x i32> @sub_ashr_and_i32_vec_undef(<4 x i32> %x, <4 x i32> %y) {
-; CHECK-LABEL: @sub_ashr_and_i32_vec_undef(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 undef>
-; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
+define <4 x i32> @sub_ashr_and_i32_vec_poison(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @sub_ashr_and_i32_vec_poison(
+; CHECK-NEXT:    [[ISNEG:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> [[X]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nsw <4 x i32> %y, %x
-  %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 undef>
+  %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 poison>
   %and = and <4 x i32> %shr, %x
   ret <4 x i32> %and
 }