[llvm] 3b071e1 - [InstCombine] add tests for signbit-smear; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-08-27T08:04:35-04:00
New Revision: 3b071e1d5df7b68e0cd06456b0adbf7a6faba8f2

URL: https://github.com/llvm/llvm-project/commit/3b071e1d5df7b68e0cd06456b0adbf7a6faba8f2
DIFF: https://github.com/llvm/llvm-project/commit/3b071e1d5df7b68e0cd06456b0adbf7a6faba8f2.diff

LOG: [InstCombine] add tests for signbit-smear; NFC

issue #57381

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/negated-bitmask.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/negated-bitmask.ll b/llvm/test/Transforms/InstCombine/negated-bitmask.ll
index c8270fe009850..ba53c2483acdf 100644
--- a/llvm/test/Transforms/InstCombine/negated-bitmask.ll
+++ b/llvm/test/Transforms/InstCombine/negated-bitmask.ll
@@ -184,5 +184,125 @@ define <2 x i32> @neg_mask1_lshr_extrause_lshr(<2 x i32> %a0) {
   ret <2 x i32> %neg
 }
 
+define i32 @neg_signbit(i8 %x) {
+; CHECK-LABEL: @neg_signbit(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 7
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[S]] to i32
+; CHECK-NEXT:    [[R:%.*]] = sub nsw i32 0, [[Z]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = lshr i8 %x, 7
+  %z = zext i8 %s to i32
+  %r = sub i32 0, %z
+  ret i32 %r
+}
+
+define <2 x i64> @neg_signbit_use1(<2 x i32> %x) {
+; CHECK-LABEL: @neg_signbit_use1(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 31, i32 poison>
+; CHECK-NEXT:    call void @usev2i32(<2 x i32> [[S]])
+; CHECK-NEXT:    [[Z:%.*]] = zext <2 x i32> [[S]] to <2 x i64>
+; CHECK-NEXT:    [[R:%.*]] = sub nsw <2 x i64> zeroinitializer, [[Z]]
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %s = lshr <2 x i32> %x, <i32 31, i32 poison>
+  call void @usev2i32(<2 x i32> %s)
+  %z = zext <2 x i32> %s to <2 x i64>
+  %r = sub <2 x i64> zeroinitializer, %z
+  ret <2 x i64> %r
+}
+
+define i8 @neg_signbit_use2(i5 %x) {
+; CHECK-LABEL: @neg_signbit_use2(
+; CHECK-NEXT:    [[S:%.*]] = lshr i5 [[X:%.*]], 4
+; CHECK-NEXT:    [[Z:%.*]] = zext i5 [[S]] to i8
+; CHECK-NEXT:    call void @usei8(i8 [[Z]])
+; CHECK-NEXT:    [[R:%.*]] = sub nsw i8 0, [[Z]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %s = lshr i5 %x, 4
+  %z = zext i5 %s to i8
+  call void @usei8(i8 %z)
+  %r = sub i8 0, %z
+  ret i8 %r
+}
+
+define i32 @neg_not_signbit1(i8 %x) {
+; CHECK-LABEL: @neg_not_signbit1(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[X:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 7
+; CHECK-NEXT:    [[R:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = lshr i8 %x, 7
+  %z = zext i8 %s to i32
+  %r = sub i32 1, %z
+  ret i32 %r
+}
+
+define i32 @neg_not_signbit2(i8 %x) {
+; CHECK-LABEL: @neg_not_signbit2(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 6
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[S]] to i32
+; CHECK-NEXT:    [[R:%.*]] = sub nsw i32 0, [[Z]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = lshr i8 %x, 6
+  %z = zext i8 %s to i32
+  %r = sub i32 0, %z
+  ret i32 %r
+}
+
+define i32 @neg_not_signbit3(i8 %x) {
+; CHECK-LABEL: @neg_not_signbit3(
+; CHECK-NEXT:    [[S:%.*]] = ashr i8 [[X:%.*]], 7
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[S]] to i32
+; CHECK-NEXT:    [[R:%.*]] = sub nsw i32 0, [[Z]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = ashr i8 %x, 7
+  %z = zext i8 %s to i32
+  %r = sub i32 0, %z
+  ret i32 %r
+}
+
+define i32 @neg_mask(i32 %x, i16 %y) {
+; CHECK-LABEL: @neg_mask(
+; CHECK-NEXT:    [[S:%.*]] = sext i16 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nsw i32 [[X:%.*]], [[S]]
+; CHECK-NEXT:    [[SH:%.*]] = lshr i16 [[Y]], 15
+; CHECK-NEXT:    [[Z:%.*]] = zext i16 [[SH]] to i32
+; CHECK-NEXT:    [[SUB2:%.*]] = sub nsw i32 0, [[Z]]
+; CHECK-NEXT:    [[R:%.*]] = and i32 [[SUB1]], [[SUB2]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = sext i16 %y to i32
+  %sub1 = sub nsw i32 %x, %s
+  %sh = lshr i16 %y, 15
+  %z = zext i16 %sh to i32
+  %sub2 = sub nsw i32 0, %z
+  %r = and i32 %sub1, %sub2
+  ret i32 %r
+}
+
+define i32 @neg_mask_const(i16 %x) {
+; CHECK-LABEL: @neg_mask_const(
+; CHECK-NEXT:    [[S:%.*]] = sext i16 [[X:%.*]] to i32
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nsw i32 1000, [[S]]
+; CHECK-NEXT:    [[SH:%.*]] = lshr i16 [[X]], 15
+; CHECK-NEXT:    [[Z:%.*]] = zext i16 [[SH]] to i32
+; CHECK-NEXT:    [[SUB2:%.*]] = sub nsw i32 0, [[Z]]
+; CHECK-NEXT:    [[R:%.*]] = and i32 [[SUB1]], [[SUB2]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %s = sext i16 %x to i32
+  %sub1 = sub nsw i32 1000, %s
+  %sh = lshr i16 %x, 15
+  %z = zext i16 %sh to i32
+  %sub2 = sub nsw i32 0, %z
+  %r = and i32 %sub1, %sub2
+  ret i32 %r
+}
+
 declare void @usei8(i8)
 declare void @usev2i32(<2 x i32>)