[llvm] faf373e - [RISCV] Pre-commit tests for D132771. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 26 16:45:57 PDT 2022
Author: Craig Topper
Date: 2022-08-26T16:41:01-07:00
New Revision: faf373e526588f5d0ce50702ad5945f9b10094f8
URL: https://github.com/llvm/llvm-project/commit/faf373e526588f5d0ce50702ad5945f9b10094f8
DIFF: https://github.com/llvm/llvm-project/commit/faf373e526588f5d0ce50702ad5945f9b10094f8.diff
LOG: [RISCV] Pre-commit tests for D132771. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/setcc-logic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 0dfd1731f656..48cc03f337c7 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -294,3 +294,941 @@ define i1 @or_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signe
%and = or i1 %cmp1, %cmp2
ret i1 %and
}
+
+declare void @bar(...)
+
+define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_sge_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB13_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_sge_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB13_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB13_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sge i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_sle_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB14_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_sle_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB14_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB14_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sle i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_uge_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB15_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_uge_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB15_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB15_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp uge i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ule_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB16_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ule_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB16_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB16_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ule i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_sge_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB17_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_sge_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB17_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB17_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sge i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_sle_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB18_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB18_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_sle_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB18_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB18_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sle i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_uge_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB19_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_uge_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB19_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB19_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp uge i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ule_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: not a0, a0
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB20_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB20_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ule_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: not a0, a0
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB20_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB20_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ule i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_sge_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB21_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB21_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_sge_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB21_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB21_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sge i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_sle_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB22_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB22_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_sle_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB22_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB22_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sle i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_uge_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB23_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB23_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_uge_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB23_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB23_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp uge i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_ule_eq:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB24_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_ule_eq:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: seqz a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB24_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB24_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ule i32 %0, %1
+ %6 = icmp eq i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_sge_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB25_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_sge_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB25_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB25_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sge i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_sle_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB26_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_sle_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB26_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB26_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp sle i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_uge_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB27_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB27_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_uge_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB27_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB27_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp uge i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: or_ule_ne:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: xor a1, a2, a3
+; RV32I-NEXT: snez a1, a1
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB28_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: or_ule_ne:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: xori a0, a0, 1
+; RV64I-NEXT: xor a1, a2, a3
+; RV64I-NEXT: snez a1, a1
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB28_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB28_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ule i32 %0, %1
+ %6 = icmp ne i32 %2, %3
+ %7 = or i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_eq_sge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slt a1, a2, a3
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB29_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_eq_sge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slt a1, a2, a3
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB29_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB29_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp eq i32 %0, %1
+ %6 = icmp sge i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_eq_sle:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slt a1, a3, a2
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB30_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB30_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_eq_sle:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slt a1, a3, a2
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB30_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB30_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp eq i32 %0, %1
+ %6 = icmp sle i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_eq_uge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: sltu a1, a2, a3
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB31_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB31_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_eq_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: sltu a1, a2, a3
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB31_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB31_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp eq i32 %0, %1
+ %6 = icmp uge i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_eq_ule:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: sltu a1, a3, a2
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB32_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB32_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_eq_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: sltu a1, a3, a2
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB32_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB32_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp eq i32 %0, %1
+ %6 = icmp ule i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ne_sge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: slt a1, a2, a3
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB33_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB33_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ne_sge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: slt a1, a2, a3
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB33_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB33_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ne i32 %0, %1
+ %6 = icmp sge i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ne_sle:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: slt a1, a3, a2
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB34_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB34_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ne_sle:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: slt a1, a3, a2
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB34_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB34_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ne i32 %0, %1
+ %6 = icmp sle i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ne_uge:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: sltu a1, a2, a3
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB35_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB35_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ne_uge:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: sltu a1, a2, a3
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB35_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB35_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ne i32 %0, %1
+ %6 = icmp uge i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
+
+define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
+; RV32I-LABEL: and_ne_ule:
+; RV32I: # %bb.0:
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: sltu a1, a3, a2
+; RV32I-NEXT: xori a1, a1, 1
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB36_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB36_2:
+; RV32I-NEXT: tail bar at plt
+;
+; RV64I-LABEL: and_ne_ule:
+; RV64I: # %bb.0:
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: sltu a1, a3, a2
+; RV64I-NEXT: xori a1, a1, 1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB36_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB36_2:
+; RV64I-NEXT: tail bar at plt
+ %5 = icmp ne i32 %0, %1
+ %6 = icmp ule i32 %2, %3
+ %7 = and i1 %5, %6
+ br i1 %7, label %9, label %8
+
+8: ; preds = %4
+ tail call void @bar()
+ br label %9
+
+9: ; preds = %8, %4
+ ret void
+}
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