[PATCH] D132718: [LoongArch] Combine add + shl to alsl.[w/d/wu]

[Gong LingQin via Phabricator via llvm-commits]

gonglingqin added a comment.

In D132718#3751016 <https://reviews.llvm.org/D132718#3751016>, @xen0n wrote:

> For the patch title: not all shifted additions can be expressed with `alsl.*` due to the limited imm range, so we could say `Combine eligible add + shl ...` to better convey the meaning.
>
> Also you could add some more tests covering other possible choices of the imm, and one negative test case showing non-powers-of-2 multipliers are not covered. It may or may not be complete (that would probably cause the testcase number to explode), just some coverage would be nice.

Thanks, I will modify the title of the patch and add testcases.



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Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:737
 
+/// Shift and add
+let Predicates = [IsLA32] in {
----------------
xen0n wrote:
> "Shifted addition"?
Thanks, I will change it.


================
Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:745
+          (ALSL_D GPR:$rj, GPR:$rk, uimm2_plus1:$imm2)>;
+def : Pat<(loongarch_bstrpick (add GPR:$rk, (shl GPR:$rj, uimm2_plus1:$imm2)),
+                              (i64 31), (i64 0)),
----------------
xen0n wrote:
> This feels a bit weird, could a more generic node be used here instead of the rather concrete `bstrpick` one?
Since `zero_extend` will be converted to `and`, and the `and` node generates `LoongArchISD::BSTRPICK` by combining before the instruction selection process. Therefore, if common nodes are used for matching, optimization needs to be added during the Combine process, which requires more code. So tblgen was chosen to simplify the code.


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https://reviews.llvm.org/D132718