[PATCH] D132190: [AArch64][GlobalISel] Legalize G_SHUFFLE_VECTOR with different lengths

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:951
+
+  if (Mask.size() <= SrcNumElts)
+    return false;
----------------
might want a TODO here so we can see it ought to be supported?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:958
+
+  auto Undef = MIRBuilder.buildUndef(SrcTy);
+  SmallVector<Register, 8> MOps1(NumConcat, Undef.getReg(0));
----------------
can we have a comment here which, at a high level, describes the general legalization algorithm/approach?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:971
+    int Idx = Mask[I];
+    if (Idx >= (int)SrcNumElts)
+      Idx -= SrcNumElts - PaddedMaskNumElts;
----------------
static_cast for greppability?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132190/new/

https://reviews.llvm.org/D132190