[PATCH] D132674: [RISCV][M68k] Replace fixed size BitVector with std::bittest.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: reames, asb, myhsu.
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Saves a heap allocation and avoids an explicit call to the BitVector constructor.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132674

Files:
  llvm/lib/Target/M68k/M68kSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp


Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -91,7 +91,8 @@
                                StringRef TuneCPU, StringRef FS,
                                StringRef ABIName, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
-      FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
+      FrameLowering(
+          initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
Index: llvm/lib/Target/M68k/M68kSubtarget.cpp
===================================================================
--- llvm/lib/Target/M68k/M68kSubtarget.cpp
+++ llvm/lib/Target/M68k/M68kSubtarget.cpp
@@ -50,8 +50,7 @@
 
 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              const M68kTargetMachine &TM)
-    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
-      TM(TM), TSInfo(),
+    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
       InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
       FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
       TargetTriple(TT) {


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