[llvm] ca5f8b0 - [RISCV][CostModel] Correct typo in saturating intrinsic names
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 25 09:11:23 PDT 2022
Author: Philip Reames
Date: 2022-08-25T09:10:22-07:00
New Revision: ca5f8b09090de56b3423ffdb162d09ec4d8d4f2f
URL: https://github.com/llvm/llvm-project/commit/ca5f8b09090de56b3423ffdb162d09ec4d8d4f2f
DIFF: https://github.com/llvm/llvm-project/commit/ca5f8b09090de56b3423ffdb162d09ec4d8d4f2f.diff
LOG: [RISCV][CostModel] Correct typo in saturating intrinsic names
The fact that we silently accept unrecognized intrinsic names is sometimes a bit annoying.
Added:
Modified:
llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll b/llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll
index 2ec80870d00d..bf886bdf7e87 100644
--- a/llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/int-sat-math.ll
@@ -1,680 +1,680 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v | FileCheck %s
-define void @sadd_sat() {
-; CHECK-LABEL: 'sadd_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.sadd_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.sadd_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.sadd_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.sadd_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.sadd_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.sadd_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.sadd_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.sadd_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.sadd_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.sadd_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.sadd_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.sadd_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.sadd_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.sadd_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.sadd_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.sadd_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.sadd_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.sadd_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.sadd_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.sadd_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.sadd_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.sadd_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.sadd_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.sadd_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.sadd_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.sadd_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.sadd_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.sadd_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.sadd_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.sadd_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.sadd_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.sadd_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.sadd_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.sadd_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.sadd_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @sadd.sat() {
+; CHECK-LABEL: 'sadd.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %1 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %2 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %3 = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %4 = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %5 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %6 = call <vscale x 2 x i8> @llvm.sadd.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %7 = call <vscale x 4 x i8> @llvm.sadd.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %8 = call <vscale x 8 x i8> @llvm.sadd.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %9 = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %10 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %11 = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %12 = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %13 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %14 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %15 = call <vscale x 2 x i16> @llvm.sadd.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %16 = call <vscale x 4 x i16> @llvm.sadd.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %17 = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %18 = call <vscale x 16 x i16> @llvm.sadd.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %19 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %20 = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %21 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %22 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %23 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %24 = call <vscale x 2 x i32> @llvm.sadd.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %25 = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %26 = call <vscale x 8 x i32> @llvm.sadd.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %27 = call <vscale x 16 x i32> @llvm.sadd.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %28 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %29 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %30 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %31 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %32 = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %33 = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %34 = call <vscale x 4 x i64> @llvm.sadd.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %35 = call <vscale x 8 x i64> @llvm.sadd.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.sadd_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.sadd_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.sadd_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.sadd_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.sadd_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.sadd_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.sadd_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.sadd_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.sadd_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.sadd_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.sadd_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.sadd_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.sadd_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.sadd_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.sadd_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.sadd_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.sadd_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.sadd_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.sadd_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.sadd_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.sadd_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.sadd_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.sadd_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.sadd_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.sadd_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.sadd_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.sadd_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.sadd_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.sadd_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.sadd_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.sadd_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.sadd_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.sadd_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.sadd_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.sadd_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.sadd.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.sadd.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.sadd.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.sadd.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.sadd.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.sadd.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.sadd.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.sadd.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.sadd.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.sadd.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.sadd.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.sadd.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.sadd.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.sadd.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.sadd.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-define void @uadd_sat() {
-; CHECK-LABEL: 'uadd_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.uadd_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.uadd_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.uadd_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.uadd_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.uadd_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.uadd_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.uadd_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.uadd_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.uadd_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.uadd_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.uadd_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.uadd_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.uadd_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.uadd_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.uadd_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.uadd_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.uadd_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.uadd_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.uadd_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.uadd_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.uadd_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.uadd_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.uadd_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.uadd_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.uadd_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.uadd_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.uadd_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.uadd_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.uadd_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.uadd_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.uadd_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.uadd_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.uadd_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.uadd_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.uadd_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @uadd.sat() {
+; CHECK-LABEL: 'uadd.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %1 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %2 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %3 = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %4 = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %5 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %6 = call <vscale x 2 x i8> @llvm.uadd.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %7 = call <vscale x 4 x i8> @llvm.uadd.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %8 = call <vscale x 8 x i8> @llvm.uadd.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %9 = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %10 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %12 = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %13 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %14 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %15 = call <vscale x 2 x i16> @llvm.uadd.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %16 = call <vscale x 4 x i16> @llvm.uadd.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %17 = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %18 = call <vscale x 16 x i16> @llvm.uadd.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %19 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %20 = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %21 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %22 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %23 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %24 = call <vscale x 2 x i32> @llvm.uadd.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %25 = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %26 = call <vscale x 8 x i32> @llvm.uadd.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %27 = call <vscale x 16 x i32> @llvm.uadd.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %28 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %29 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %30 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %31 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %32 = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %33 = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %34 = call <vscale x 4 x i64> @llvm.uadd.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %35 = call <vscale x 8 x i64> @llvm.uadd.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.uadd_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.uadd_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.uadd_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.uadd_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.uadd_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.uadd_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.uadd_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.uadd_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.uadd_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.uadd_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.uadd_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.uadd_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.uadd_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.uadd_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.uadd_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.uadd_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.uadd_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.uadd_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.uadd_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.uadd_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.uadd_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.uadd_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.uadd_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.uadd_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.uadd_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.uadd_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.uadd_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.uadd_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.uadd_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.uadd_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.uadd_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.uadd_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.uadd_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.uadd_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.uadd_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.uadd.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.uadd.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.uadd.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.uadd.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.uadd.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.uadd.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.uadd.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.uadd.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.uadd.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.uadd.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.uadd.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.uadd.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.uadd.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.uadd.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.uadd.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-define void @usub_sat() {
-; CHECK-LABEL: 'usub_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.usub_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.usub_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.usub_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.usub_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.usub_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.usub_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.usub_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.usub_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.usub_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.usub_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.usub_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.usub_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.usub_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.usub_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.usub_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.usub_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.usub_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.usub_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.usub_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.usub_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.usub_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.usub_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.usub_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.usub_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.usub_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.usub_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.usub_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.usub_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.usub_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.usub_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.usub_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.usub_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.usub_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.usub_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.usub_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @usub.sat() {
+; CHECK-LABEL: 'usub.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %1 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %2 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %3 = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %4 = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %5 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %6 = call <vscale x 2 x i8> @llvm.usub.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %7 = call <vscale x 4 x i8> @llvm.usub.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %8 = call <vscale x 8 x i8> @llvm.usub.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %9 = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %10 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %12 = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %13 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %14 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %15 = call <vscale x 2 x i16> @llvm.usub.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %16 = call <vscale x 4 x i16> @llvm.usub.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %17 = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %18 = call <vscale x 16 x i16> @llvm.usub.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %19 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %20 = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %21 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %22 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %23 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %24 = call <vscale x 2 x i32> @llvm.usub.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %25 = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %26 = call <vscale x 8 x i32> @llvm.usub.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %27 = call <vscale x 16 x i32> @llvm.usub.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %28 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %29 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %30 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %31 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %32 = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %33 = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %34 = call <vscale x 4 x i64> @llvm.usub.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %35 = call <vscale x 8 x i64> @llvm.usub.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.usub_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.usub_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.usub_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.usub_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.usub_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.usub_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.usub_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.usub_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.usub_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.usub_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.usub_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.usub_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.usub_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.usub_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.usub_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.usub_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.usub_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.usub_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.usub_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.usub_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.usub_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.usub_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.usub_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.usub_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.usub_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.usub_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.usub_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.usub_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.usub_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.usub_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.usub_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.usub_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.usub_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.usub_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.usub_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.usub.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.usub.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.usub.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.usub.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.usub.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.usub.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.usub.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.usub.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.usub.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.usub.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.usub.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.usub.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.usub.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.usub.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.usub.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.usub.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.usub.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.usub.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-define void @ssub_sat() {
-; CHECK-LABEL: 'ssub_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.ssub_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.ssub_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.ssub_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.ssub_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.ssub_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.ssub_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.ssub_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.ssub_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.ssub_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.ssub_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.ssub_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.ssub_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.ssub_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.ssub_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.ssub_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.ssub_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.ssub_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.ssub_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.ssub_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.ssub_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.ssub_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.ssub_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.ssub_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.ssub_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.ssub_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.ssub_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.ssub_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.ssub_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.ssub_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.ssub_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.ssub_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.ssub_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.ssub_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.ssub_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.ssub_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @ssub.sat() {
+; CHECK-LABEL: 'ssub.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %1 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %2 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %3 = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %4 = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %5 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %6 = call <vscale x 2 x i8> @llvm.ssub.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %7 = call <vscale x 4 x i8> @llvm.ssub.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %8 = call <vscale x 8 x i8> @llvm.ssub.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %9 = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %10 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %11 = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %12 = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %13 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %14 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %15 = call <vscale x 2 x i16> @llvm.ssub.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %16 = call <vscale x 4 x i16> @llvm.ssub.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %17 = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %18 = call <vscale x 16 x i16> @llvm.ssub.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %19 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %20 = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %21 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %22 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %23 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %24 = call <vscale x 2 x i32> @llvm.ssub.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %25 = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %26 = call <vscale x 8 x i32> @llvm.ssub.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %27 = call <vscale x 16 x i32> @llvm.ssub.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %28 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %29 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %30 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %31 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %32 = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %33 = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %34 = call <vscale x 4 x i64> @llvm.ssub.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %35 = call <vscale x 8 x i64> @llvm.ssub.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.ssub_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.ssub_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.ssub_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.ssub_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.ssub_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.ssub_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.ssub_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.ssub_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.ssub_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.ssub_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.ssub_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.ssub_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.ssub_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.ssub_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.ssub_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.ssub_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.ssub_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.ssub_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.ssub_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.ssub_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.ssub_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.ssub_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.ssub_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.ssub_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.ssub_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.ssub_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.ssub_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.ssub_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.ssub_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.ssub_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.ssub_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.ssub_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.ssub_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.ssub_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.ssub_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.ssub.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.ssub.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.ssub.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.ssub.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.ssub.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.ssub.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.ssub.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.ssub.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.ssub.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.ssub.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.ssub.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.ssub.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.ssub.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.ssub.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.ssub.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-define void @ushl_sat() {
-; CHECK-LABEL: 'ushl_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.ushl_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.ushl_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.ushl_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.ushl_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.ushl_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.ushl_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.ushl_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.ushl_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.ushl_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.ushl_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.ushl_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.ushl_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.ushl_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.ushl_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.ushl_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.ushl_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.ushl_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.ushl_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.ushl_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.ushl_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.ushl_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.ushl_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.ushl_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.ushl_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.ushl_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.ushl_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.ushl_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.ushl_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.ushl_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.ushl_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.ushl_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.ushl_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.ushl_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.ushl_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.ushl_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @ushl.sat() {
+; CHECK-LABEL: 'ushl.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.ushl.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.ushl.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.ushl.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.ushl.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.ushl.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.ushl.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.ushl.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.ushl.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.ushl.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.ushl.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.ushl.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.ushl.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.ushl.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.ushl.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.ushl.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.ushl.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.ushl.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.ushl.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.ushl.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.ushl.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.ushl.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.ushl.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.ushl.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.ushl.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.ushl.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.ushl.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.ushl.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.ushl.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.ushl.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.ushl_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.ushl_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.ushl_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.ushl_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.ushl_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.ushl_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.ushl_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.ushl_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.ushl_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.ushl_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.ushl_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.ushl_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.ushl_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.ushl_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.ushl_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.ushl_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.ushl_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.ushl_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.ushl_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.ushl_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.ushl_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.ushl_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.ushl_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.ushl_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.ushl_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.ushl_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.ushl_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.ushl_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.ushl_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.ushl_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.ushl_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.ushl_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.ushl_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.ushl_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.ushl_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.ushl.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.ushl.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.ushl.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.ushl.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.ushl.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.ushl.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.ushl.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.ushl.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.ushl.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.ushl.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.ushl.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.ushl.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.ushl.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.ushl.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.ushl.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.ushl.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.ushl.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.ushl.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.ushl.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.ushl.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.ushl.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.ushl.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.ushl.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.ushl.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.ushl.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.ushl.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.ushl.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.ushl.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.ushl.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-define void @sshl_sat() {
-; CHECK-LABEL: 'sshl_sat'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.sshl_sat.i8(i8 undef, i8 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.sshl_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.sshl_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.sshl_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.sshl_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.sshl_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.sshl_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.sshl_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.sshl_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.sshl_sat.i16(i16 undef, i16 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.sshl_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.sshl_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.sshl_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.sshl_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.sshl_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.sshl_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.sshl_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.sshl_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.sshl_sat.i32(i32 undef, i32 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.sshl_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.sshl_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.sshl_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.sshl_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.sshl_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.sshl_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.sshl_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.sshl_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.sshl_sat.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.sshl_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.sshl_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.sshl_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.sshl_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.sshl_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.sshl_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
-; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.sshl_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+define void @sshl.sat() {
+; CHECK-LABEL: 'sshl.sat'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i8 @llvm.sshl.sat.i8(i8 undef, i8 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <2 x i8> @llvm.sshl.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = call <4 x i8> @llvm.sshl.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <8 x i8> @llvm.sshl.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 2 x i8> @llvm.sshl.sat.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 4 x i8> @llvm.sshl.sat.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 8 x i8> @llvm.sshl.sat.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call i16 @llvm.sshl.sat.i16(i16 undef, i16 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %12 = call <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %13 = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %14 = call <16 x i16> @llvm.sshl.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %15 = call <vscale x 2 x i16> @llvm.sshl.sat.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 4 x i16> @llvm.sshl.sat.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 16 x i16> @llvm.sshl.sat.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call i32 @llvm.sshl.sat.i32(i32 undef, i32 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %20 = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %21 = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %22 = call <8 x i32> @llvm.sshl.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %23 = call <16 x i32> @llvm.sshl.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %24 = call <vscale x 2 x i32> @llvm.sshl.sat.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %25 = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %26 = call <vscale x 8 x i32> @llvm.sshl.sat.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %27 = call <vscale x 16 x i32> @llvm.sshl.sat.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call i64 @llvm.sshl.sat.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %29 = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %30 = call <4 x i64> @llvm.sshl.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %31 = call <8 x i64> @llvm.sshl.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %32 = call <16 x i64> @llvm.sshl.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %33 = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %34 = call <vscale x 4 x i64> @llvm.sshl.sat.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+; CHECK-NEXT: Cost Model: Invalid cost for instruction: %35 = call <vscale x 8 x i64> @llvm.sshl.sat.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
- call i8 @llvm.sshl_sat.i8(i8 undef, i8 undef)
- call <2 x i8> @llvm.sshl_sat.v2i8(<2 x i8> undef, <2 x i8> undef)
- call <4 x i8> @llvm.sshl_sat.v4i8(<4 x i8> undef, <4 x i8> undef)
- call <8 x i8> @llvm.sshl_sat.v8i8(<8 x i8> undef, <8 x i8> undef)
- call <16 x i8> @llvm.sshl_sat.v16i8(<16 x i8> undef, <16 x i8> undef)
- call <vscale x 2 x i8> @llvm.sshl_sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
- call <vscale x 4 x i8> @llvm.sshl_sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
- call <vscale x 8 x i8> @llvm.sshl_sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
- call <vscale x 16 x i8> @llvm.sshl_sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
- call i16 @llvm.sshl_sat.i16(i16 undef, i16 undef)
- call <2 x i16> @llvm.sshl_sat.v2i16(<2 x i16> undef, <2 x i16> undef)
- call <4 x i16> @llvm.sshl_sat.v4i16(<4 x i16> undef, <4 x i16> undef)
- call <8 x i16> @llvm.sshl_sat.v8i16(<8 x i16> undef, <8 x i16> undef)
- call <16 x i16> @llvm.sshl_sat.v16i16(<16 x i16> undef, <16 x i16> undef)
- call <vscale x 2 x i16> @llvm.sshl_sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
- call <vscale x 4 x i16> @llvm.sshl_sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
- call <vscale x 8 x i16> @llvm.sshl_sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
- call <vscale x 16 x i16> @llvm.sshl_sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
- call i32 @llvm.sshl_sat.i32(i32 undef, i32 undef)
- call <2 x i32> @llvm.sshl_sat.v2i32(<2 x i32> undef, <2 x i32> undef)
- call <4 x i32> @llvm.sshl_sat.v4i32(<4 x i32> undef, <4 x i32> undef)
- call <8 x i32> @llvm.sshl_sat.v8i32(<8 x i32> undef, <8 x i32> undef)
- call <16 x i32> @llvm.sshl_sat.v16i32(<16 x i32> undef, <16 x i32> undef)
- call <vscale x 2 x i32> @llvm.sshl_sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
- call <vscale x 4 x i32> @llvm.sshl_sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
- call <vscale x 8 x i32> @llvm.sshl_sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
- call <vscale x 16 x i32> @llvm.sshl_sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
- call i64 @llvm.sshl_sat.i64(i64 undef, i64 undef)
- call <2 x i64> @llvm.sshl_sat.v2i64(<2 x i64> undef, <2 x i64> undef)
- call <4 x i64> @llvm.sshl_sat.v4i64(<4 x i64> undef, <4 x i64> undef)
- call <8 x i64> @llvm.sshl_sat.v8i64(<8 x i64> undef, <8 x i64> undef)
- call <16 x i64> @llvm.sshl_sat.v16i64(<16 x i64> undef, <16 x i64> undef)
- call <vscale x 2 x i64> @llvm.sshl_sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
- call <vscale x 4 x i64> @llvm.sshl_sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
- call <vscale x 8 x i64> @llvm.sshl_sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
+ call i8 @llvm.sshl.sat.i8(i8 undef, i8 undef)
+ call <2 x i8> @llvm.sshl.sat.v2i8(<2 x i8> undef, <2 x i8> undef)
+ call <4 x i8> @llvm.sshl.sat.v4i8(<4 x i8> undef, <4 x i8> undef)
+ call <8 x i8> @llvm.sshl.sat.v8i8(<8 x i8> undef, <8 x i8> undef)
+ call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> undef, <16 x i8> undef)
+ call <vscale x 2 x i8> @llvm.sshl.sat.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef)
+ call <vscale x 4 x i8> @llvm.sshl.sat.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef)
+ call <vscale x 8 x i8> @llvm.sshl.sat.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef)
+ call <vscale x 16 x i8> @llvm.sshl.sat.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+ call i16 @llvm.sshl.sat.i16(i16 undef, i16 undef)
+ call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> undef, <2 x i16> undef)
+ call <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16> undef, <4 x i16> undef)
+ call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> undef, <8 x i16> undef)
+ call <16 x i16> @llvm.sshl.sat.v16i16(<16 x i16> undef, <16 x i16> undef)
+ call <vscale x 2 x i16> @llvm.sshl.sat.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef)
+ call <vscale x 4 x i16> @llvm.sshl.sat.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef)
+ call <vscale x 8 x i16> @llvm.sshl.sat.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef)
+ call <vscale x 16 x i16> @llvm.sshl.sat.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef)
+ call i32 @llvm.sshl.sat.i32(i32 undef, i32 undef)
+ call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
+ call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
+ call <8 x i32> @llvm.sshl.sat.v8i32(<8 x i32> undef, <8 x i32> undef)
+ call <16 x i32> @llvm.sshl.sat.v16i32(<16 x i32> undef, <16 x i32> undef)
+ call <vscale x 2 x i32> @llvm.sshl.sat.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef)
+ call <vscale x 4 x i32> @llvm.sshl.sat.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef)
+ call <vscale x 8 x i32> @llvm.sshl.sat.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef)
+ call <vscale x 16 x i32> @llvm.sshl.sat.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i32> undef)
+ call i64 @llvm.sshl.sat.i64(i64 undef, i64 undef)
+ call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+ call <4 x i64> @llvm.sshl.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+ call <8 x i64> @llvm.sshl.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+ call <16 x i64> @llvm.sshl.sat.v16i64(<16 x i64> undef, <16 x i64> undef)
+ call <vscale x 2 x i64> @llvm.sshl.sat.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef)
+ call <vscale x 4 x i64> @llvm.sshl.sat.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef)
+ call <vscale x 8 x i64> @llvm.sshl.sat.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> undef)
ret void
}
-declare i8 @llvm.sadd_sat.i8(i8, i8)
-declare <2 x i8> @llvm.sadd_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.sadd_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.sadd_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.sadd_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.sadd_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.sadd_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.sadd_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.sadd_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.sadd_sat.i16(i16, i16)
-declare <2 x i16> @llvm.sadd_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.sadd_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.sadd_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.sadd_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.sadd_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.sadd_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.sadd_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.sadd_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.sadd_sat.i32(i32, i32)
-declare <2 x i32> @llvm.sadd_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.sadd_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.sadd_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.sadd_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.sadd_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.sadd_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.sadd_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.sadd_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.sadd_sat.i64(i64, i64)
-declare <2 x i64> @llvm.sadd_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.sadd_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.sadd_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.sadd_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.sadd_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.sadd_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.sadd_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.sadd.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.sadd.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.sadd.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.sadd.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.sadd.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.sadd.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.sadd.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.sadd.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.sadd.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.sadd.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.sadd.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.sadd.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.sadd.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.sadd.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.sadd.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
-declare i8 @llvm.uadd_sat.i8(i8, i8)
-declare <2 x i8> @llvm.uadd_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.uadd_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.uadd_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.uadd_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.uadd_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.uadd_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.uadd_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.uadd_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.uadd_sat.i16(i16, i16)
-declare <2 x i16> @llvm.uadd_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.uadd_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.uadd_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.uadd_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.uadd_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.uadd_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.uadd_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.uadd_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.uadd_sat.i32(i32, i32)
-declare <2 x i32> @llvm.uadd_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.uadd_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.uadd_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.uadd_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.uadd_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.uadd_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.uadd_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.uadd_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.uadd_sat.i64(i64, i64)
-declare <2 x i64> @llvm.uadd_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.uadd_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.uadd_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.uadd_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.uadd_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.uadd_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.uadd_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.uadd.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.uadd.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.uadd.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.uadd.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.uadd.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.uadd.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.uadd.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.uadd.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.uadd.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.uadd.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.uadd.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.uadd.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.uadd.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.uadd.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.uadd.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
-declare i8 @llvm.usub_sat.i8(i8, i8)
-declare <2 x i8> @llvm.usub_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.usub_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.usub_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.usub_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.usub_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.usub_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.usub_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.usub_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.usub_sat.i16(i16, i16)
-declare <2 x i16> @llvm.usub_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.usub_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.usub_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.usub_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.usub_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.usub_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.usub_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.usub_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.usub_sat.i32(i32, i32)
-declare <2 x i32> @llvm.usub_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.usub_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.usub_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.usub_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.usub_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.usub_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.usub_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.usub_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.usub_sat.i64(i64, i64)
-declare <2 x i64> @llvm.usub_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.usub_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.usub_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.usub_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.usub_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.usub_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.usub_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.usub.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.usub.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.usub.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.usub.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.usub.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.usub.sat.i16(i16, i16)
+declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.usub.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.usub.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.usub.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.usub.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.usub.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.usub.sat.i32(i32, i32)
+declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.usub.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.usub.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.usub.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.usub.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.usub.sat.i64(i64, i64)
+declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.usub.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.usub.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.usub.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.usub.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.usub.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.usub.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
-declare i8 @llvm.ssub_sat.i8(i8, i8)
-declare <2 x i8> @llvm.ssub_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.ssub_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.ssub_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.ssub_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.ssub_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.ssub_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.ssub_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.ssub_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.ssub_sat.i16(i16, i16)
-declare <2 x i16> @llvm.ssub_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.ssub_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.ssub_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.ssub_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.ssub_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.ssub_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.ssub_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.ssub_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.ssub_sat.i32(i32, i32)
-declare <2 x i32> @llvm.ssub_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.ssub_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.ssub_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.ssub_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.ssub_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.ssub_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.ssub_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.ssub_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.ssub_sat.i64(i64, i64)
-declare <2 x i64> @llvm.ssub_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.ssub_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.ssub_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.ssub_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.ssub_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.ssub_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.ssub_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.ssub.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.ssub.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.ssub.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.ssub.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.ssub.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.ssub.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.ssub.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.ssub.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.ssub.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.ssub.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.ssub.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.ssub.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.ssub.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.ssub.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.ssub.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
-declare i8 @llvm.ushl_sat.i8(i8, i8)
-declare <2 x i8> @llvm.ushl_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.ushl_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.ushl_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.ushl_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.ushl_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.ushl_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.ushl_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.ushl_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.ushl_sat.i16(i16, i16)
-declare <2 x i16> @llvm.ushl_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.ushl_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.ushl_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.ushl_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.ushl_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.ushl_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.ushl_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.ushl_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.ushl_sat.i32(i32, i32)
-declare <2 x i32> @llvm.ushl_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.ushl_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.ushl_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.ushl_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.ushl_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.ushl_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.ushl_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.ushl_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.ushl_sat.i64(i64, i64)
-declare <2 x i64> @llvm.ushl_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.ushl_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.ushl_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.ushl_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.ushl_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.ushl_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.ushl_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.ushl.sat.i8(i8, i8)
+declare <2 x i8> @llvm.ushl.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.ushl.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.ushl.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.ushl.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.ushl.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.ushl.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.ushl.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.ushl.sat.i16(i16, i16)
+declare <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.ushl.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.ushl.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.ushl.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.ushl.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.ushl.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.ushl.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.ushl.sat.i32(i32, i32)
+declare <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.ushl.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.ushl.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.ushl.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.ushl.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.ushl.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.ushl.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.ushl.sat.i64(i64, i64)
+declare <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.ushl.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.ushl.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.ushl.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.ushl.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.ushl.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.ushl.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
-declare i8 @llvm.sshl_sat.i8(i8, i8)
-declare <2 x i8> @llvm.sshl_sat.v2i8(<2 x i8>, <2 x i8>)
-declare <4 x i8> @llvm.sshl_sat.v4i8(<4 x i8>, <4 x i8>)
-declare <8 x i8> @llvm.sshl_sat.v8i8(<8 x i8>, <8 x i8>)
-declare <16 x i8> @llvm.sshl_sat.v16i8(<16 x i8>, <16 x i8>)
-declare <vscale x 2 x i8> @llvm.sshl_sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
-declare <vscale x 4 x i8> @llvm.sshl_sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
-declare <vscale x 8 x i8> @llvm.sshl_sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 16 x i8> @llvm.sshl_sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare i16 @llvm.sshl_sat.i16(i16, i16)
-declare <2 x i16> @llvm.sshl_sat.v2i16(<2 x i16>, <2 x i16>)
-declare <4 x i16> @llvm.sshl_sat.v4i16(<4 x i16>, <4 x i16>)
-declare <8 x i16> @llvm.sshl_sat.v8i16(<8 x i16>, <8 x i16>)
-declare <16 x i16> @llvm.sshl_sat.v16i16(<16 x i16>, <16 x i16>)
-declare <vscale x 2 x i16> @llvm.sshl_sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 4 x i16> @llvm.sshl_sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 8 x i16> @llvm.sshl_sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 16 x i16> @llvm.sshl_sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
-declare i32 @llvm.sshl_sat.i32(i32, i32)
-declare <2 x i32> @llvm.sshl_sat.v2i32(<2 x i32>, <2 x i32>)
-declare <4 x i32> @llvm.sshl_sat.v4i32(<4 x i32>, <4 x i32>)
-declare <8 x i32> @llvm.sshl_sat.v8i32(<8 x i32>, <8 x i32>)
-declare <16 x i32> @llvm.sshl_sat.v16i32(<16 x i32>, <16 x i32>)
-declare <vscale x 2 x i32> @llvm.sshl_sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i32> @llvm.sshl_sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 8 x i32> @llvm.sshl_sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 16 x i32> @llvm.sshl_sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
-declare i64 @llvm.sshl_sat.i64(i64, i64)
-declare <2 x i64> @llvm.sshl_sat.v2i64(<2 x i64>, <2 x i64>)
-declare <4 x i64> @llvm.sshl_sat.v4i64(<4 x i64>, <4 x i64>)
-declare <8 x i64> @llvm.sshl_sat.v8i64(<8 x i64>, <8 x i64>)
-declare <16 x i64> @llvm.sshl_sat.v16i64(<16 x i64>, <16 x i64>)
-declare <vscale x 2 x i64> @llvm.sshl_sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-declare <vscale x 4 x i64> @llvm.sshl_sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-declare <vscale x 8 x i64> @llvm.sshl_sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
+declare i8 @llvm.sshl.sat.i8(i8, i8)
+declare <2 x i8> @llvm.sshl.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <4 x i8> @llvm.sshl.sat.v4i8(<4 x i8>, <4 x i8>)
+declare <8 x i8> @llvm.sshl.sat.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>)
+declare <vscale x 2 x i8> @llvm.sshl.sat.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
+declare <vscale x 4 x i8> @llvm.sshl.sat.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
+declare <vscale x 8 x i8> @llvm.sshl.sat.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
+declare <vscale x 16 x i8> @llvm.sshl.sat.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
+declare i16 @llvm.sshl.sat.i16(i16, i16)
+declare <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16>, <2 x i16>)
+declare <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.sshl.sat.v16i16(<16 x i16>, <16 x i16>)
+declare <vscale x 2 x i16> @llvm.sshl.sat.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
+declare <vscale x 4 x i16> @llvm.sshl.sat.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
+declare <vscale x 8 x i16> @llvm.sshl.sat.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 16 x i16> @llvm.sshl.sat.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
+declare i32 @llvm.sshl.sat.i32(i32, i32)
+declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.sshl.sat.v8i32(<8 x i32>, <8 x i32>)
+declare <16 x i32> @llvm.sshl.sat.v16i32(<16 x i32>, <16 x i32>)
+declare <vscale x 2 x i32> @llvm.sshl.sat.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.sshl.sat.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.sshl.sat.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.sshl.sat.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare i64 @llvm.sshl.sat.i64(i64, i64)
+declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.sshl.sat.v4i64(<4 x i64>, <4 x i64>)
+declare <8 x i64> @llvm.sshl.sat.v8i64(<8 x i64>, <8 x i64>)
+declare <16 x i64> @llvm.sshl.sat.v16i64(<16 x i64>, <16 x i64>)
+declare <vscale x 2 x i64> @llvm.sshl.sat.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
+declare <vscale x 4 x i64> @llvm.sshl.sat.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
+declare <vscale x 8 x i64> @llvm.sshl.sat.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
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