[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh updated this revision to Diff 455514.
Pierre-vh added a comment.

It compiles now, but it still does not print vcc_lo for wave32.ll and I'm not sure what else to try.
I spent a while comparing the detailed records of TableGen and found no major difference. I also tried
looking for example instructions that have this w32 variant (like v_cmp_lt) and found no special-casing anywhere in the codebase, so
i'm not sure what to do


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
  llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
  llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
  llvm/test/CodeGen/AMDGPU/frem.ll
  llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
  llvm/test/CodeGen/AMDGPU/llvm.powi.ll
  llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/wave32.ll

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