[llvm] 5364f49 - Fix CSR update check

[Matthias Braun via llvm-commits]

Author: Matthias Braun
Date: 2022-08-24T18:09:49-07:00
New Revision: 5364f4940711561b8c0a549c39c654413b704c28

URL: https://github.com/llvm/llvm-project/commit/5364f4940711561b8c0a549c39c654413b704c28
DIFF: https://github.com/llvm/llvm-project/commit/5364f4940711561b8c0a549c39c654413b704c28.diff

LOG: Fix CSR update check

D132080 introduced a bug leading to `RegisterClassInfo` caches not
getting invalidated when there was exactly one more CSR register added.

Differential Revision: https://reviews.llvm.org/D132606

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterClassInfo.cpp
    llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
    llvm/test/CodeGen/XCore/scavenging.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index faed78e0117f1..fba8c35ecec26 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -60,10 +60,14 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
     CSRChanged = false;
     size_t LastSize = LastCalleeSavedRegs.size();
     for (unsigned I = 0;; ++I) {
-      if (CSR[I] == 0 || I >= LastSize) {
+      if (CSR[I] == 0) {
         CSRChanged = I != LastSize;
         break;
       }
+      if (I >= LastSize) {
+        CSRChanged = true;
+        break;
+      }
       if (CSR[I] != LastCalleeSavedRegs[I]) {
         CSRChanged = true;
         break;

diff  --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
index 270de9a055900..c65a202e21087 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
@@ -101,6 +101,7 @@ entry:
 define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) local_unnamed_addr {
 ; CHECK-ALL-LABEL: X2IsCallerSaved:
 ; CHECK-S:         .localentry X2IsCallerSaved, 1
+; CHECK-P9-NOT:    .localentry
 ; CHECK-ALL:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill

diff  --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index 1c9f78be7eb5b..adf313e4a9890 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -55,52 +55,51 @@ declare void @g(i32*, i32*)
 ; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
 ; CHECK: .p2align  2
 ; CHECK: [[ARG5:.LCPI[0-9_]+]]:
-; CHECK: .long   100002
+; CHECK: .long   100003
 ; CHECK: [[INDEX0:.LCPI[0-9_]+]]:
-; CHECK: .long   100004
-; CHECK: [[INDEX1:.LCPI[0-9_]+]]:
 ; CHECK: .long   80002
-; CHECK: [[INDEX2:.LCPI[0-9_]+]]:
+; CHECK: [[INDEX1:.LCPI[0-9_]+]]:
 ; CHECK: .long   81002
-; CHECK: [[INDEX3:.LCPI[0-9_]+]]:
+; CHECK: [[INDEX2:.LCPI[0-9_]+]]:
 ; CHECK: .long   82002
-; CHECK: [[INDEX4:.LCPI[0-9_]+]]:
+; CHECK: [[INDEX3:.LCPI[0-9_]+]]:
 ; CHECK: .long   83002
-; CHECK: [[INDEX5:.LCPI[0-9_]+]]:
+; CHECK: [[INDEX4:.LCPI[0-9_]+]]:
 ; CHECK: .long   84002
 ; CHECK: .text
 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
 ; CHECK-LABEL: ScavengeSlots:
 ; CHECK: entsp 65535
-; CHECK: extsp 34468
+; CHECK: extsp 34467
 ; scavenge r11
 ; CHECK: ldaw r11, sp[0]
 ; scavenge r4 using SR spill slot
 ; CHECK: stw r4, sp[1]
 ; CHECK: ldw r4, cp[[[ARG5]]]
 ; r11 used to load 5th argument
-; CHECK: stw r10, r11[r4]
-; CHECK: ldaw r10, sp[0]
-; CHECK: ldw r11, cp[[[INDEX0]]]
-; CHECK: ldw r10, r10[r11]
-; CHECK: ldaw r11, sp[0]
-; CHECK: ldw r4, cp[[[INDEX1]]]
-; CHECK: stw r0, r11[r4]
+; CHECK: ldw r11, r11[r4]
+; CHECK: ldaw r4, sp[0]
+; scavenge r5 using SR spill slot
+; CHECK: stw r5, sp[0]
+; CHECK: ldw r5, cp[[[INDEX0]]]
+; r4 & r5 used by InsertSPConstInst() to emit STW_l3r instruction.
+; CHECK: stw r0, r4[r5]
+; CHECK: ldaw r0, sp[0]
+; CHECK: ldw r5, cp[[[INDEX1]]]
+; CHECK: stw r1, r0[r5]
 ; CHECK: ldaw r0, sp[0]
-; CHECK: ldw r11, cp[[[INDEX2]]]
-; CHECK: stw r1, r0[r11]
+; CHECK: ldw r1, cp[[[INDEX2]]]
+; CHECK: stw r2, r0[r1]
 ; CHECK: ldaw r0, sp[0]
 ; CHECK: ldw r1, cp[[[INDEX3]]]
 ; CHECK: stw r3, r0[r1]
 ; CHECK: ldaw r0, sp[0]
-; CHECK: ldw r1, cp[[[INDEX5]]]
-; CHECK: stw r10, r0[r1]
-; CHECK: ldaw r10, sp[0]
-; CHECK: ldw r0, cp[[[ARG5]]]
-; CHECK: ldw r10, r10[r0]
+; CHECK: ldw r1, cp[[[INDEX4]]]
+; CHECK: stw r11, r0[r1]
 ; CHECK: ldaw sp, sp[65535]
 ; CHECK: ldw r4, sp[1]
-; CHECK: retsp 34468
+; CHECK: ldw r5, sp[0]
+; CHECK: retsp 34467
 define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
 entry:
   %Data = alloca [100000 x i32]