[PATCH] D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions.
Andrei Safronov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 18:06:23 PDT 2022
andreisfr updated this revision to Diff 455445.
andreisfr added a comment.
Update according to changes in MEMW, EXTW, DSYNC, ESYNC, ISYNC and RSYNC instruction descriptions
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D64834/new/
https://reviews.llvm.org/D64834
Files:
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaOperands.td
llvm/test/MC/Xtensa/xtensa-invalid.s
llvm/test/MC/Xtensa/xtensa-valid.s
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D64834.455445.patch
Type: text/x-patch
Size: 34858 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220825/c14456e6/attachment.bin>
More information about the llvm-commits
mailing list