[PATCH] D132573: [AArch64 - SVE]: Use SVE to lower reduce.fadd.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1384-1385
+    // NEON doesn't support across-vector reductions, but SVE does.
+    for (auto VT : {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32, MVT::v1f64,
+                    MVT::v2f64})
+      setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
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This is quite a limited set of types. I wonder if it actually supports VECREDUCE_SEQ_FADD for e.g. <8 x float> when the vector length is 256, or <8 x double> when the vector length is 512. Can you try this out?

Some other code in this file iterates through all possible FP/integer values and uses `useSVEForFixedLengthVectorVT()` to determine whether SVE should be used. This function has an option named `OverrideNEON`, which you can use to make it work for 128bit vectors.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fadd-reduce.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mattr=+sve -mtriple=aarch64  %s -o - | FileCheck %s --check-prefixes=CHECK
+
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Could you also add some RUN lines for other vector lengths?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D132573/new/

https://reviews.llvm.org/D132573