[PATCH] D131962: [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI

[Alexander Richardson via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
arichardson marked an inline comment as done.
Closed by commit rG38107171ed56: [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI (authored by arichardson).

Changed prior to commit:
  https://reviews.llvm.org/D131962?vs=452996&id=455199#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131962/new/

https://reviews.llvm.org/D131962

Files:
  llvm/include/llvm/Target/Target.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.h
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
  llvm/lib/Target/Mips/MipsRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.h
  llvm/lib/Target/Mips/MipsRegisterInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/VE/VERegisterInfo.cpp
  llvm/lib/Target/VE/VERegisterInfo.h
  llvm/lib/Target/VE/VERegisterInfo.td
  llvm/utils/TableGen/CodeGenRegisters.cpp
  llvm/utils/TableGen/CodeGenRegisters.h
  llvm/utils/TableGen/RegisterInfoEmitter.cpp

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