[PATCH] D132552: [AMDGPU][CodeGen] Support (base | offset) SMEM loads.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

As a follow up could we update all calls to getBaseWithConstantOffset to pass in a non-null KnownBits?



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp:44
 
+  if (mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) && KnownBits &&
+      KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
----------------
Test `KnownBits` first because it's cheapest.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1989
   // wraparound, because s_load instructions perform the addition in 64 bits.
-  if (Addr.getValueType() == MVT::i32 && !Addr->getFlags().hasNoUnsignedWrap())
+  if (Addr.getValueType() == MVT::i32 && Addr.getOpcode() == ISD::ADD &&
+      !Addr->getFlags().hasNoUnsignedWrap())
----------------
Nice catch!


================
Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:113
 
+; GCN-LABEL: name: test_buffer_load_sgpr_or_imm_offset
+; SDAG-DAG: %[[BASE0:.*]]:sgpr_32 = COPY $sgpr0
----------------
Please precommit this new test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132552/new/

https://reviews.llvm.org/D132552