[llvm] 8c1f18b - [RISCV] : Add support for immediate operands.
Zhang Qing Shan via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 24 02:49:00 PDT 2022
Author: MarkGoncharovAl
Date: 2022-08-24T17:48:39+08:00
New Revision: 8c1f18bd3ee1fbd19a83c16ea2038c771cb82b97
URL: https://github.com/llvm/llvm-project/commit/8c1f18bd3ee1fbd19a83c16ea2038c771cb82b97
DIFF: https://github.com/llvm/llvm-project/commit/8c1f18bd3ee1fbd19a83c16ea2038c771cb82b97.diff
LOG: [RISCV] : Add support for immediate operands.
llvm-exegesis uses operand type information provided in tablegen files to initialize
immediate arguments of the instruction. Some of them simply don't have such information.
Thus we should set into relevant immediate operands their specific type.
Also create verification methods for them.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D131771
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index fa408f7fc5d7d..aa5e817fd15eb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -219,11 +219,23 @@ enum OperandType : unsigned {
OPERAND_UIMM4,
OPERAND_UIMM5,
OPERAND_UIMM7,
+ OPERAND_UIMM7_LSB00,
+ OPERAND_UIMM8_LSB00,
+ OPERAND_UIMM8_LSB000,
OPERAND_UIMM12,
+ OPERAND_ZERO,
+ OPERAND_SIMM5,
+ OPERAND_SIMM5_PLUS1,
+ OPERAND_SIMM6,
+ OPERAND_SIMM6_NONZERO,
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_UIMM20,
OPERAND_UIMMLOG2XLEN,
+ OPERAND_UIMMLOG2XLEN_NONZERO,
+ OPERAND_UIMM_SHFL,
+ OPERAND_VTYPEI10,
+ OPERAND_VTYPEI11,
OPERAND_RVKRNUM,
OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
// Operand is either a register or uimm5, this is used by V extension pseudo
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 06d3e207008fc..aad7098a4595c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1153,9 +1153,39 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_UIMM(4)
CASE_OPERAND_UIMM(5)
CASE_OPERAND_UIMM(7)
+ case RISCVOp::OPERAND_UIMM7_LSB00:
+ Ok = isShiftedUInt<5, 2>(Imm);
+ break;
+ case RISCVOp::OPERAND_UIMM8_LSB00:
+ Ok = isShiftedUInt<6, 2>(Imm);
+ break;
+ case RISCVOp::OPERAND_UIMM8_LSB000:
+ Ok = isShiftedUInt<5, 3>(Imm);
+ break;
CASE_OPERAND_UIMM(12)
CASE_OPERAND_UIMM(20)
// clang-format on
+ case RISCVOp::OPERAND_ZERO:
+ Ok = Imm == 0;
+ break;
+ case RISCVOp::OPERAND_SIMM5:
+ Ok = isInt<5>(Imm);
+ break;
+ case RISCVOp::OPERAND_SIMM5_PLUS1:
+ Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+ break;
+ case RISCVOp::OPERAND_SIMM6:
+ Ok = isInt<6>(Imm);
+ break;
+ case RISCVOp::OPERAND_SIMM6_NONZERO:
+ Ok = Imm != 0 && isInt<6>(Imm);
+ break;
+ case RISCVOp::OPERAND_VTYPEI10:
+ Ok = isUInt<10>(Imm);
+ break;
+ case RISCVOp::OPERAND_VTYPEI11:
+ Ok = isUInt<11>(Imm);
+ break;
case RISCVOp::OPERAND_SIMM12:
Ok = isInt<12>(Imm);
break;
@@ -1163,10 +1193,17 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedInt<7, 5>(Imm);
break;
case RISCVOp::OPERAND_UIMMLOG2XLEN:
- if (STI.getTargetTriple().isArch64Bit())
- Ok = isUInt<6>(Imm);
- else
- Ok = isUInt<5>(Imm);
+ Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
+ : isUInt<5>(Imm);
+ break;
+ case RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO:
+ Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
+ : isUInt<5>(Imm);
+ Ok = Ok && Imm != 0;
+ break;
+ case RISCVOp::OPERAND_UIMM_SHFL:
+ Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<5>(Imm)
+ : isUInt<4>(Imm);
break;
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index f3ca460c15caf..80e7c4ce8c850 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -26,6 +26,8 @@ def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
// TODO: should ensure invalid shamt is rejected when decoding.
let DecoderMethod = "decodeUImmOperand<6>";
+ let OperandType = "OPERAND_UIMMLOG2XLEN_NONZERO";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -40,6 +42,8 @@ def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<6>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<6>";
+ let OperandType = "OPERAND_SIMM6";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
@@ -53,6 +57,8 @@ def simm6nonzero : Operand<XLenVT>,
let ParserMatchClass = SImmAsmOperand<6, "NonZero">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<6>";
+ let OperandType = "OPERAND_SIMM6_NONZERO";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
@@ -64,6 +70,8 @@ def simm6nonzero : Operand<XLenVT>,
def immzero : Operand<XLenVT>,
ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
let ParserMatchClass = ImmZeroAsmOperand;
+ let OperandType = "OPERAND_ZERO";
+ let OperandNamespace = "RISCVOp";
}
def CLUIImmAsmOperand : AsmOperandClass {
@@ -100,6 +108,8 @@ def uimm7_lsb00 : Operand<XLenVT>,
let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeUImmOperand<7>";
+ let OperandType = "OPERAND_UIMM7_LSB00";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -114,6 +124,8 @@ def uimm8_lsb00 : Operand<XLenVT>,
let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeUImmOperand<8>";
+ let OperandType = "OPERAND_UIMM8_LSB00";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -128,6 +140,8 @@ def uimm8_lsb000 : Operand<XLenVT>,
let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeUImmOperand<8>";
+ let OperandType = "OPERAND_UIMM8_LSB000";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 7a2701e1e6703..81da7503d15e9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -28,6 +28,14 @@ class VTypeIOp<int VTypeINum> : Operand<XLenVT> {
let ParserMatchClass = VTypeIAsmOperand<VTypeINum>;
let PrintMethod = "printVTypeI";
let DecoderMethod = "decodeUImmOperand<"#VTypeINum#">";
+ let OperandType = "OPERAND_VTYPEI" # VTypeINum;
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isUInt<VTypeINum>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
}
def VTypeIOp10 : VTypeIOp<10>;
@@ -54,6 +62,8 @@ def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<5>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<5>";
+ let OperandType = "OPERAND_SIMM5";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
@@ -71,6 +81,8 @@ def SImm5Plus1AsmOperand : AsmOperandClass {
def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
let ParserMatchClass = SImm5Plus1AsmOperand;
+ let OperandType = "OPERAND_SIMM5_PLUS1";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 5bf6148d462c5..ebcc38b8aecda 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -71,6 +71,8 @@ def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
}]> {
let ParserMatchClass = UImmLog2XLenHalfAsmOperand;
let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_UIMM_SHFL";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
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