[llvm] d51581f - [RISCV][TableGen] Mark MachineInstr with FrameIndex as not compressible

[ZHU Zijia via llvm-commits]

Author: ZHU Zijia
Date: 2022-08-24T13:23:38+08:00
New Revision: d51581ff2c3ef5355a52a7445c1fe40fe83e5be0

URL: https://github.com/llvm/llvm-project/commit/d51581ff2c3ef5355a52a7445c1fe40fe83e5be0
DIFF: https://github.com/llvm/llvm-project/commit/d51581ff2c3ef5355a52a7445c1fe40fe83e5be0.diff

LOG: [RISCV][TableGen] Mark MachineInstr with FrameIndex as not compressible

If a MachineInstr's operand should be Reg in compiler's output but is
currently FrameIndex, `isCompressibleInst()` will terminate at
`MachineOperandType::getReg()`.

This patch adds `.isReg()` checks to make `isCompressibleInst()` return
false for these MachineInstr, allowing `getInstSizeInBytes()` to return
a value and `EstimateFunctionSizeInBytes()` to work as intended.

See https://reviews.llvm.org/D129999#3694222 for details.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D129999

Added: 
    

Modified: 
    llvm/test/TableGen/AsmPredicateCombiningRISCV.td
    llvm/utils/TableGen/CompressInstEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
index 2e9458be4703..b0df1b3c82ee 100644
--- a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
+++ b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
@@ -60,6 +60,7 @@ def BigInst : RVInst<1, [AsmPred1]>;
 def SmallInst1 : RVInst16<1, []>;
 def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
 // COMPRESS:      if (STI.getFeatureBits()[arch::AsmCond1] &&
+// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
 // COMPRESS-NEXT: // SmallInst1 $r
 
@@ -67,12 +68,14 @@ def SmallInst2 : RVInst16<2, []>;
 def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
 // COMPRESS:      if (STI.getFeatureBits()[arch::AsmCond2a] &&
 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
+// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
 // COMPRESS-NEXT: // SmallInst2 $r
 
 def SmallInst3 : RVInst16<2, []>;
 def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
 // COMPRESS:      if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
+// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
 // COMPRESS-NEXT: // SmallInst3 $r
 
@@ -81,6 +84,7 @@ def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>
 // COMPRESS:      if (STI.getFeatureBits()[arch::AsmCond1] &&
 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
+// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
 // COMPRESS-NEXT: // SmallInst4 $r
 
@@ -88,6 +92,7 @@ def SmallInst5 : RVInst16<2, []>;
 def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
 // COMPRESS:      if (STI.getFeatureBits()[arch::AsmCond1] &&
 // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
+// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
 // COMPRESS-NEXT: // SmallInst5 $r
 

diff  --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 1fd85939e74e..a1dab412c583 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -716,7 +716,10 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
         if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
           CondStream.indent(6)
-              << "(MI.getOperand(" << OpNo << ").getReg() ==  MI.getOperand("
+              << "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand("
+              << SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n"
+              << "      (MI.getOperand(" << OpNo
+              << ").getReg() ==  MI.getOperand("
               << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
         else
           PrintFatalError("Unexpected tied operand types!\n");
@@ -735,7 +738,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
       case OpData::Reg: {
         Record *Reg = SourceOperandMap[OpNo].Data.Reg;
         CondStream.indent(6)
-            << "(MI.getOperand(" << OpNo << ").getReg() == " << TargetName
+            << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
+            << "      (MI.getOperand(" << OpNo << ").getReg() == " << TargetName
             << "::" << Reg->getName() << ") &&\n";
         break;
       }
@@ -759,10 +763,12 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
           // Don't check register class if this is a tied operand, it was done
           // for the operand its tied to.
           if (DestOperand.getTiedRegister() == -1)
-            CondStream.indent(6) << "(MRI.getRegClass(" << TargetName
-                                 << "::" << DestOperand.Rec->getName()
-                                 << "RegClassID).contains(MI.getOperand("
-                                 << OpIdx << ").getReg())) &&\n";
+            CondStream.indent(6)
+                << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
+                << "      (MRI.getRegClass(" << TargetName
+                << "::" << DestOperand.Rec->getName()
+                << "RegClassID).contains(MI.getOperand(" << OpIdx
+                << ").getReg())) &&\n";
 
           if (CompressOrUncompress)
             CodeStream.indent(6)