[llvm] e624f8a - [DAG] MatchRotate - bail if we fail to match a shl/srl pair

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-08-24T03:05:07+01:00
New Revision: e624f8a3bb88075493dec521408993ea0ef7bde0

URL: https://github.com/llvm/llvm-project/commit/e624f8a3bb88075493dec521408993ea0ef7bde0
DIFF: https://github.com/llvm/llvm-project/commit/e624f8a3bb88075493dec521408993ea0ef7bde0.diff

LOG: [DAG] MatchRotate - bail if we fail to match a shl/srl pair

extractShiftForRotate may fail to return canonicalized shifts due to constant folding or other simplification that can occur in getNode()

Fixes Issue #57283

Added: 
    llvm/test/CodeGen/X86/pr57283.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 07fb54e95af0..752d02ba07cf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7642,6 +7642,10 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
     std::swap(LHSMask, RHSMask);
   }
 
+  // Something has gone wrong - we've lost the shl/srl pair - bail.
+  if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
+    return SDValue();
+
   unsigned EltSizeInBits = VT.getScalarSizeInBits();
   SDValue LHSShiftArg = LHSShift.getOperand(0);
   SDValue LHSShiftAmt = LHSShift.getOperand(1);

diff  --git a/llvm/test/CodeGen/X86/pr57283.ll b/llvm/test/CodeGen/X86/pr57283.ll
new file mode 100644
index 000000000000..58e1432cc329
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr57283.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
+
+define void @PR57283() nounwind {
+; X86-LABEL: PR57283:
+; X86:       # %bb.0: # %BB
+; X86-NEXT:    pushl %ebp
+; X86-NEXT:    movl %esp, %ebp
+; X86-NEXT:    andl $-8, %esp
+; X86-NEXT:    subl $16, %esp
+; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl $0, (%esp)
+; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %ebp, %esp
+; X86-NEXT:    popl %ebp
+; X86-NEXT:    retl
+;
+; X64-LABEL: PR57283:
+; X64:       # %bb.0: # %BB
+; X64-NEXT:    movq $0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movq $0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    retq
+BB:
+  %A6 = alloca i64, align 8
+  %A = alloca i64, align 8
+  %L = load i64, i64* %A, align 4
+  %B3 = sub i64 %L, %L
+  %B2 = mul i64 %B3, 4294967296
+  %B1 = add i64 %B2, %B2
+  %B4 = udiv i64 %B2, -9223372036854775808
+  %B = xor i64 %B1, %B4
+  store i64 %B, i64* %A, align 4
+  %B5 = sdiv i64 %B, -1
+  store i64 %B5, i64* %A6, align 4
+  ret void
+}