[PATCH] D131340: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

smd added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1678-1679
 
+let Predicates = [IsRV64], Uses = [ X5 ],
+                           Defs = [ X1, X6, X7, X28, X29, X30, X31 ] in {
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
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jrtc27 wrote:
> smd wrote:
> > jrtc27 wrote:
> > > This formatting is not used anywhere in the RISCV backend
> > Should be fixed now, thanks.
> It is not
Could you please check this kind of formatting?
If you still find it wrong could you please suggest the proper one, thanks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131340/new/

https://reviews.llvm.org/D131340