[PATCH] D131343: [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

smd added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:451
+
+    // Intentionally load the GOT entry and branch to it, rather than possibly
+    // late binding the function, which may clobber the registers before we have
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jrtc27 wrote:
> This is what STO_RISCV_VARIANT_CC is for
If you don't mind, I'd like address that in a separate patch, as I have to go through the discussion on this matter. Thanks


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Comment at: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll:1
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s
+
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jrtc27 wrote:
> Use update_llc_test_checks.py. Also test PIC too if you have PIC-specific code.
Fixed, thanks


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Comment at: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll:3
+
+target triple = "riscv64-unknown-linux"
+
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jrtc27 wrote:
> Redundant, you have -mtriple in the command line
Fixed, thanks


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D131343/new/

https://reviews.llvm.org/D131343